*CONTROL RECT 1 PHASE Full-wave 171910201043 NABILA DINDA 2020 UNEJ

Waiting for data

Signal	Value
Signal	Value

Cursor 1	Cursor 2	∆X	1/∆X	∆Y	∆Y (Phase)

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

ID:

x10

x0.1

Sheet:1

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SPICE

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SPICE Netlist

This is a text-based representation of the circuit.
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Probes do not appear in netlists.

** CONTROL RECT 1 PHASE Full-wave 171910201043 NABILA DINDA 2020 UNEJ **
*
* Multisim Live SPICE netlist
*
*

* --- Circuit Topology ---

* Component: C1
cC1 1 0 0.0001

* Component: L1
lL1 4 3 0.1

* Component: R1
rR1 5 2 100000 VIRTUAL_RESISTANCE_R1

* Component: S1
xS1 1 5 SPST_Switch_S1 Params: Ron=0.0001 Roff=100000000 State=0

* Component: S2
xS2 0 2 SPST_Switch_S2 Params: Ron=0.0001 Roff=100000000 State=1

* Component: S3
xS3 0 3 SPST_Switch_S3 Params: Ron=0.0001 Roff=100000000 State=0

* Component: S4
xS4 5 4 2 SPDT_Switch_S4 Params: Ron=0.0001 Roff=100000000 State=1

* Component: SCR_A
xSCR_A 6 5 9 SCR_IDEAL_SCR_A PARAMS: Vth=2.5 Ih=0.01 Vfscr=0 Ron=0.01 Roff=10000000

* Component: SCR_A1
xSCR_A1 0 6 8 SCR_IDEAL_SCR_A1 PARAMS: Vth=2.5 Ih=0.01 Vfscr=0 Ron=0.01 Roff=10000000

* Component: SCR_B
xSCR_B 7 5 8 SCR_IDEAL_SCR_B PARAMS: Vth=2.5 Ih=0.01 Vfscr=0 Ron=0.01 Roff=10000000

* Component: SCR_B1
xSCR_B1 0 7 9 SCR_IDEAL_SCR_B1 PARAMS: Vth=2.5 Ih=0.01 Vfscr=0 Ron=0.01 Roff=10000000

* Component: U1
xU1 6 7 11 9 8 PHASEANGLE_FULL_U1 PARAMS: frequency=60 pulse_width=20 pulse_amplitude=120

* Component: V1
vV1 6 7 dc 0 ac 1 0
+ distof1 0 0
+ distof2 0 0
+ sin ( 0 120 50 0 0 0 )

* Component: V2
vV2 11 0 dc 20 ac 0 0
+ distof1 0 0
+ distof2 0 0

* --- Circuit Models ---

* R1 model
.model VIRTUAL_RESISTANCE_R1 r( )

* --- Subcircuits ---

* S1 subcircuit
.subckt SPST_Switch_S1 port1 port2 Params: Ron=1e-8 Roff=1e30 State=0
V2 state 0 DC {State}
R1 state 6 10
V1 6 0 DC 0
W0 port2 port1 V1 NC_contact
.model NC_contact ISWITCH (Ion=0.05 Ioff=0.025 Ron={Ron} Roff={Roff})
.ends

* S2 subcircuit
.subckt SPST_Switch_S2 port1 port2 Params: Ron=1e-8 Roff=1e30 State=0
V2 state 0 DC {State}
R1 state 6 10
V1 6 0 DC 0
W0 port2 port1 V1 NC_contact
.model NC_contact ISWITCH (Ion=0.05 Ioff=0.025 Ron={Ron} Roff={Roff})
.ends

* S3 subcircuit
.subckt SPST_Switch_S3 port1 port2 Params: Ron=1e-8 Roff=1e30 State=0
V2 state 0 DC {State}
R1 state 6 10
V1 6 0 DC 0
W0 port2 port1 V1 NC_contact
.model NC_contact ISWITCH (Ion=0.05 Ioff=0.025 Ron={Ron} Roff={Roff})
.ends

* S4 subcircuit
.subckt SPDT_Switch_S4 port1 port2 port3 Params: Ron=1e-8 Roff=1e30 State=0
V2 state 0 DC {State}
R1 state 6 10
V1 6 0 DC 0
W0 port2 port1 V1 NC_contact
W1 port2 port3 V1 NO_contact
.MODEL NO_contact ISWITCH (ION=0.05 IOFF=0.025 RON={Ron} ROFF={Roff})
.MODEL NC_contact ISWITCH (ION=0.05 IOFF=0.025 RON={Roff} ROFF={Ron})
.ends

* SCR_A subcircuit
.subckt SCR_IDEAL_SCR_A Anode Cathode Gate PARAMS: Vth=2.5 Ih=0 Vfscr=0 Ron=1m Roff=1meg
E3 a2 0 Value = { if(I(vIscr)<=Ih,5,0) }

vIscr Anode 10 dc 0

xU6 8 cathode DIODE_IDEAL params: Vf={Vfscr} Rd={Ron/2} Rdoff={Roff/2}
.subckt DIODE_IDEAL a k params: Vf=0 Rd=1m Rdoff=1meg
ad1 %vd(a k) %id(a k) diode1
.model diode1 pwl(x_array=[{Vf-1} {Vf} {Vf+1}] y_array=[{-1/Rdoff} 0 {1/Rd}] fraction=false input_domain=0.0)
.ends

xS1 10 8 a3 0 VSwitchS1
.subckt VSwitchS1 1 2 3 4
S1 1 2 3 4 vsw0
.model vsw0 vswitch ( Roff={Roff/2} Ron={Ron/2} Voff=0 Von=1 )
.ends

aU5 7 d_constsource_U5
.model d_constsource_U5 d_constsource(state=1)

aU4 [a1 dU4.B dU4.C] reset AND2__TIL__1
xU4.B a2 dU4.B TIL_RCV__NON__1
xU4.C a3 dU4.C TIL_RCV__NON__1
aU3 dU3.A a1 NOT__TIL__1

xU3.A gate dU3.A TIL_RCV__NON__1_Gate

aU2 dU2.S reset 7
+ U2_OPEN_SET U2_OPEN_RESET
+ dU2.Q U2_OPEN_notQ SR_LATCH__TIL__1

xU2.S gate dU2.S TIL_RCV__NON__1_Gate

xU2.Q dU2.Q a3 TIL_DRV__NON__1

.MODEL AND2__TIL__1 d_and ( rise_delay = 1n fall_delay = 1n)
.MODEL NOT__TIL__1 d_inverter (rise_delay = 1n fall_delay = 1n)
.SUBCKT TIL_DRV__NON__1 1 2
* TIL Driver Model 1 = D/A input, 2 = out
aDACin1 [1] [2] aDAC
.MODEL aDAC dac_bridge (out_low= 0 out_high = 5 out_undef = 0)
.ENDS

.SUBCKT TIL_RCV__NON__1_Gate 1 2
* TIL Receiver Model 1 = input, 2 = A/D out
aADCin1 [1] [2] ADC
.MODEL ADC adc_bridge (in_low= {Vth} in_high = {Vth})
.ENDS

.SUBCKT TIL_RCV__NON__1 1 2
* TIL Receiver Model 1 = input, 2 = A/D out
aADCin1 [1] [2] ADC
.MODEL ADC adc_bridge (in_low= 2.5 in_high = 2.5)
.ENDS

.MODEL SR_LATCH__TIL__1 d_srlatch (sr_delay = 1n enable_delay = 1n
+ set_delay = 1n reset_delay= 1n
+ ic = 0 rise_delay = 1n fall_delay = 1n)

.ends

* SCR_A1 subcircuit
.subckt SCR_IDEAL_SCR_A1 Anode Cathode Gate PARAMS: Vth=2.5 Ih=0 Vfscr=0 Ron=1m Roff=1meg
E3 a2 0 Value = { if(I(vIscr)<=Ih,5,0) }

vIscr Anode 10 dc 0

xU6 8 cathode DIODE_IDEAL params: Vf={Vfscr} Rd={Ron/2} Rdoff={Roff/2}
.subckt DIODE_IDEAL a k params: Vf=0 Rd=1m Rdoff=1meg
ad1 %vd(a k) %id(a k) diode1
.model diode1 pwl(x_array=[{Vf-1} {Vf} {Vf+1}] y_array=[{-1/Rdoff} 0 {1/Rd}] fraction=false input_domain=0.0)
.ends

xS1 10 8 a3 0 VSwitchS1
.subckt VSwitchS1 1 2 3 4
S1 1 2 3 4 vsw0
.model vsw0 vswitch ( Roff={Roff/2} Ron={Ron/2} Voff=0 Von=1 )
.ends

aU5 7 d_constsource_U5
.model d_constsource_U5 d_constsource(state=1)

aU4 [a1 dU4.B dU4.C] reset AND2__TIL__1
xU4.B a2 dU4.B TIL_RCV__NON__1
xU4.C a3 dU4.C TIL_RCV__NON__1
aU3 dU3.A a1 NOT__TIL__1

xU3.A gate dU3.A TIL_RCV__NON__1_Gate

aU2 dU2.S reset 7
+ U2_OPEN_SET U2_OPEN_RESET
+ dU2.Q U2_OPEN_notQ SR_LATCH__TIL__1

xU2.S gate dU2.S TIL_RCV__NON__1_Gate

xU2.Q dU2.Q a3 TIL_DRV__NON__1

.MODEL AND2__TIL__1 d_and ( rise_delay = 1n fall_delay = 1n)
.MODEL NOT__TIL__1 d_inverter (rise_delay = 1n fall_delay = 1n)
.SUBCKT TIL_DRV__NON__1 1 2
* TIL Driver Model 1 = D/A input, 2 = out
aDACin1 [1] [2] aDAC
.MODEL aDAC dac_bridge (out_low= 0 out_high = 5 out_undef = 0)
.ENDS

.SUBCKT TIL_RCV__NON__1_Gate 1 2
* TIL Receiver Model 1 = input, 2 = A/D out
aADCin1 [1] [2] ADC
.MODEL ADC adc_bridge (in_low= {Vth} in_high = {Vth})
.ENDS

.SUBCKT TIL_RCV__NON__1 1 2
* TIL Receiver Model 1 = input, 2 = A/D out
aADCin1 [1] [2] ADC
.MODEL ADC adc_bridge (in_low= 2.5 in_high = 2.5)
.ENDS

.MODEL SR_LATCH__TIL__1 d_srlatch (sr_delay = 1n enable_delay = 1n
+ set_delay = 1n reset_delay= 1n
+ ic = 0 rise_delay = 1n fall_delay = 1n)

.ends

* SCR_B subcircuit
.subckt SCR_IDEAL_SCR_B Anode Cathode Gate PARAMS: Vth=2.5 Ih=0 Vfscr=0 Ron=1m Roff=1meg
E3 a2 0 Value = { if(I(vIscr)<=Ih,5,0) }

vIscr Anode 10 dc 0

xU6 8 cathode DIODE_IDEAL params: Vf={Vfscr} Rd={Ron/2} Rdoff={Roff/2}
.subckt DIODE_IDEAL a k params: Vf=0 Rd=1m Rdoff=1meg
ad1 %vd(a k) %id(a k) diode1
.model diode1 pwl(x_array=[{Vf-1} {Vf} {Vf+1}] y_array=[{-1/Rdoff} 0 {1/Rd}] fraction=false input_domain=0.0)
.ends

xS1 10 8 a3 0 VSwitchS1
.subckt VSwitchS1 1 2 3 4
S1 1 2 3 4 vsw0
.model vsw0 vswitch ( Roff={Roff/2} Ron={Ron/2} Voff=0 Von=1 )
.ends

aU5 7 d_constsource_U5
.model d_constsource_U5 d_constsource(state=1)

aU4 [a1 dU4.B dU4.C] reset AND2__TIL__1
xU4.B a2 dU4.B TIL_RCV__NON__1
xU4.C a3 dU4.C TIL_RCV__NON__1
aU3 dU3.A a1 NOT__TIL__1

xU3.A gate dU3.A TIL_RCV__NON__1_Gate

aU2 dU2.S reset 7
+ U2_OPEN_SET U2_OPEN_RESET
+ dU2.Q U2_OPEN_notQ SR_LATCH__TIL__1

xU2.S gate dU2.S TIL_RCV__NON__1_Gate

xU2.Q dU2.Q a3 TIL_DRV__NON__1

.MODEL AND2__TIL__1 d_and ( rise_delay = 1n fall_delay = 1n)
.MODEL NOT__TIL__1 d_inverter (rise_delay = 1n fall_delay = 1n)
.SUBCKT TIL_DRV__NON__1 1 2
* TIL Driver Model 1 = D/A input, 2 = out
aDACin1 [1] [2] aDAC
.MODEL aDAC dac_bridge (out_low= 0 out_high = 5 out_undef = 0)
.ENDS

.SUBCKT TIL_RCV__NON__1_Gate 1 2
* TIL Receiver Model 1 = input, 2 = A/D out
aADCin1 [1] [2] ADC
.MODEL ADC adc_bridge (in_low= {Vth} in_high = {Vth})
.ENDS

.SUBCKT TIL_RCV__NON__1 1 2
* TIL Receiver Model 1 = input, 2 = A/D out
aADCin1 [1] [2] ADC
.MODEL ADC adc_bridge (in_low= 2.5 in_high = 2.5)
.ENDS

.MODEL SR_LATCH__TIL__1 d_srlatch (sr_delay = 1n enable_delay = 1n
+ set_delay = 1n reset_delay= 1n
+ ic = 0 rise_delay = 1n fall_delay = 1n)

.ends

* SCR_B1 subcircuit
.subckt SCR_IDEAL_SCR_B1 Anode Cathode Gate PARAMS: Vth=2.5 Ih=0 Vfscr=0 Ron=1m Roff=1meg
E3 a2 0 Value = { if(I(vIscr)<=Ih,5,0) }

vIscr Anode 10 dc 0

xU6 8 cathode DIODE_IDEAL params: Vf={Vfscr} Rd={Ron/2} Rdoff={Roff/2}
.subckt DIODE_IDEAL a k params: Vf=0 Rd=1m Rdoff=1meg
ad1 %vd(a k) %id(a k) diode1
.model diode1 pwl(x_array=[{Vf-1} {Vf} {Vf+1}] y_array=[{-1/Rdoff} 0 {1/Rd}] fraction=false input_domain=0.0)
.ends

xS1 10 8 a3 0 VSwitchS1
.subckt VSwitchS1 1 2 3 4
S1 1 2 3 4 vsw0
.model vsw0 vswitch ( Roff={Roff/2} Ron={Ron/2} Voff=0 Von=1 )
.ends

aU5 7 d_constsource_U5
.model d_constsource_U5 d_constsource(state=1)

aU4 [a1 dU4.B dU4.C] reset AND2__TIL__1
xU4.B a2 dU4.B TIL_RCV__NON__1
xU4.C a3 dU4.C TIL_RCV__NON__1
aU3 dU3.A a1 NOT__TIL__1

xU3.A gate dU3.A TIL_RCV__NON__1_Gate

aU2 dU2.S reset 7
+ U2_OPEN_SET U2_OPEN_RESET
+ dU2.Q U2_OPEN_notQ SR_LATCH__TIL__1

xU2.S gate dU2.S TIL_RCV__NON__1_Gate

xU2.Q dU2.Q a3 TIL_DRV__NON__1

.MODEL AND2__TIL__1 d_and ( rise_delay = 1n fall_delay = 1n)
.MODEL NOT__TIL__1 d_inverter (rise_delay = 1n fall_delay = 1n)
.SUBCKT TIL_DRV__NON__1 1 2
* TIL Driver Model 1 = D/A input, 2 = out
aDACin1 [1] [2] aDAC
.MODEL aDAC dac_bridge (out_low= 0 out_high = 5 out_undef = 0)
.ENDS

.SUBCKT TIL_RCV__NON__1_Gate 1 2
* TIL Receiver Model 1 = input, 2 = A/D out
aADCin1 [1] [2] ADC
.MODEL ADC adc_bridge (in_low= {Vth} in_high = {Vth})
.ENDS

.SUBCKT TIL_RCV__NON__1 1 2
* TIL Receiver Model 1 = input, 2 = A/D out
aADCin1 [1] [2] ADC
.MODEL ADC adc_bridge (in_low= 2.5 in_high = 2.5)
.ENDS

.MODEL SR_LATCH__TIL__1 d_srlatch (sr_delay = 1n enable_delay = 1n
+ set_delay = 1n reset_delay= 1n
+ ic = 0 rise_delay = 1n fall_delay = 1n)

.ends

* U1 subcircuit
.subckt PHASEANGLE_FULL_U1 sync+ sync- alpha T1 T2 PARAMS: frequency=1 pulse_width=1 pulse_amplitude=1
AT1 %vd(sync+,sync-) alpha %vd(T1,0) alphamod

E1 alpha2 0 value={v(alpha)+180}
AT3 %vd(sync+,sync-) alpha2 %vd(T2,0) alphamod

.model alphamod phase_angle_controller(freq={frequency} pulse_width={pulse_width} pulse_amplitude={pulse_amplitude})
.ends

VHDL Netlist

This is a text-based representation of a digital circuit.
The -- symbols indicates a comment.
Probes and analog components do not appear in VHDL netlists.

-- This is a VHDL representation of the -- digital circuit described in the schematic. -- If the circuit described is not valid or is incomplete, -- it may result in an invalid VHDL representation. library IEEE; use IEEE.STD_LOGIC_1164.ALL; USE WORK.ALL; entity top_design is Port ( ); end top_design; architecture BEHAVIORAL of top_design is begin end BEHAVIORAL;

Errors and Warnings

Any error, warning or information messages appear below.

Item

Document

Section

Only one section is available for multisection components.

Type

Rise time

Time it takes for signal to transition from low to high.

With non-zero rise time, the signal converts to an analog signal from a digital signal.

Fall time

Time it takes for signal to transition from high to low.

With non-zero fall time, the signal converts to an analog signal from a digital signal.

Use document settings

Use logic levels settings from Document tab.

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

Type Probe

Select desired function.

Function

Use document settings

Use logic levels settings from Document tab.

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

Enter an expression here. You can combine circuit variables with functions and operators to plot an expression in the Grapher.

Available functions, constants and operators for the expression.

Source

Data origin.

…

Upload a data file here. You can view data from this file in the grapher.

Web address of the selected Source.

Warning: A popup window will appear.

Connect

Cancel

Connecting

Disconnect

Switch on to stream data from Source when simulation runs.

For data files with more than one plot, select the plot to view.

Source type

Application used to generate the Source data.

Data type

Type of simulation data in Source.

File size

Size of the referenced file. Total file size for all data plotters cannot exceed 100 MB.

Selected simulation type does not match uploaded simulation data

Data streaming is only available in interactive simulation

Instantaneous

Displays instantaneous measurements on probe during interactive simulation.

Periodic

Displays periodic measurements on probe during Interactive simulation.

Bias point(s)

Displays bias points on probe for DC Op simulation.

No items selected.

Name CONTROL RECT 1 PHASE Full-wave 171910201043 NABILA DINDA 2020 UNEJ

Type Schematic

The simulation to run. See Simulation types for more information.

Name

Title of graph. Edit as desired.

End time

Time at which the simulation stops. Does not include pauses. Simulation does not occur in real time.

Start simulation

RELTOL

Relative error tolerance. A simulation wide accuracy control used to establish convergence.

VNTOL

Absolute voltage error tolerance. Defines the minimum value for voltage where it may still be considered accurate.

ABSTOL

Absolute current error tolerance. Defines the minimum value for current where it may still be considered accurate.

ITL1

DC iteration limit. Number of iterative passes done on DC circuit equations in attempt to reach convergence in simulation.

ITL4

Upper iteration limit. Number of iterative passes done per time point, on Transient circuit equations in attempt to reach convergence in simulation.

Integration method. The numerical integration method used in transient analysis.

Temp

℃

Operating temperature. The temperature at which the entire circuit will be simulated.

Insert shunt resistance

Inserts a resistance of RSHUNT from every analog node to ground. Will aid in convergence, but alter the behavior of the circuit.

RSHUNT

Shunt resistance. This eliminates singular matrix errors that result from a lack of a DC path to ground.

Reset to default

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

Width

Sheet width in grid squares.

Height

Sheet height in grid squares.

Grid

Toggles grid display.

Net Labels

Toggles all net labels.

Component Labels

Toggles all component labels.

CONTROL RECT 1 PHASE Full-wave 171910201043 NABILA DINDA 2020 UNEJ