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JQ~QKRESETCLKSETJQ~QKRESETCLKSETJQ~QKRESETCLKSET PR4PR3PR2PR1U12V112V03LED30LED205LED10FFC24FFC16FFC11kHzclock 0/1 0/1 0/1 0/1
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ID:

ID:
x10
x0.1
Sheet:1
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** 10 a **
*
* Multisim Live SPICE netlist
*
*

* --- Circuit Topology ---

* Component: FFC
xFFC 2 2 4 FFC_NC_SET FFC_NC_RESET bridgeFFC!Q FFC_NC_~Q Digital_JKFlipFlop_FFC PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

xbridgeFFC!Q bridgeFFC!Q 1 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: FFC1
xFFC1 bridgeFFC1!J bridgeFFC1!K 4 FFC1_NC_SET FFC1_NC_RESET bridgeFFC1!Q FFC1_NC_~Q Digital_JKFlipFlop_FFC1 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

xbridgeFFC1!J bridgeFFC1!J 6 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeFFC1!K bridgeFFC1!K 6 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeFFC1!Q bridgeFFC1!Q 5 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: FFC2
xFFC2 bridgeFFC2!J bridgeFFC2!K 4 FFC2_NC_SET FFC2_NC_RESET bridgeFFC2!Q FFC2_NC_~Q Digital_JKFlipFlop_FFC2 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

xbridgeFFC2!J bridgeFFC2!J 3 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeFFC2!K bridgeFFC2!K 3 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeFFC2!Q bridgeFFC2!Q 6 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: LED1
xLED1 1 0 LED_VIRTUAL_LED1

* Component: LED2
xLED2 5 0 LED_VIRTUAL_LED2

* Component: LED3
xLED3 6 0 LED_VIRTUAL_LED3

* Component: U1
aU1 [bridgeU1!A bridgeU1!B] 2 Digital_AND2_U1

xbridgeU1!A bridgeU1!A 5 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU1!B bridgeU1!B 6 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: V1
vV1 3 0 dc 12 ac 0 0
+ distof1 0 0
+ distof2 0 0

* Component: clock
xclock 4 Digital_Clock_clock PARAMS: Frequency=1000 Duty=50 Delay=0


* --- Circuit Models ---

* U1 model
.model Digital_AND2_U1 d_and (rise_delay=1e-9 fall_delay=1e-9)


* --- Subcircuits ---

* FFC subcircuit
.subckt Digital_JKFlipFlop_FFC 1 2 3 4 5 6 7 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n

aDG1 neg_SR initSR
aDG2 neg_clk initCLK
A1 [4 neg_SR] set xorset
A2 [3 neg_clk] clk xorclk
A3 [5 neg_SR] reset xorreset
A4 1 2 clk set reset 6 7 JK_FF
**MODELS USED*
.model initCLK d_constsource(State={Negative_Edge_Clock})
.model initSR d_constsource(State={Negative_SET_RESET})
.model xorset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorclk d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorreset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.MODEL JK_FF d_jkff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS

* FFC1 subcircuit
.subckt Digital_JKFlipFlop_FFC1 1 2 3 4 5 6 7 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n

aDG1 neg_SR initSR
aDG2 neg_clk initCLK
A1 [4 neg_SR] set xorset
A2 [3 neg_clk] clk xorclk
A3 [5 neg_SR] reset xorreset
A4 1 2 clk set reset 6 7 JK_FF
**MODELS USED*
.model initCLK d_constsource(State={Negative_Edge_Clock})
.model initSR d_constsource(State={Negative_SET_RESET})
.model xorset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorclk d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorreset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.MODEL JK_FF d_jkff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS

* FFC2 subcircuit
.subckt Digital_JKFlipFlop_FFC2 1 2 3 4 5 6 7 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n

aDG1 neg_SR initSR
aDG2 neg_clk initCLK
A1 [4 neg_SR] set xorset
A2 [3 neg_clk] clk xorclk
A3 [5 neg_SR] reset xorreset
A4 1 2 clk set reset 6 7 JK_FF
**MODELS USED*
.model initCLK d_constsource(State={Negative_Edge_Clock})
.model initSR d_constsource(State={Negative_SET_RESET})
.model xorset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorclk d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorreset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.MODEL JK_FF d_jkff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS

* LED1 subcircuit
.subckt LED_VIRTUAL_LED1 A K

dd1 A 0vNode ledDiodeModel
.model ledDiodeModel D( IS=1e-14 N=1 RS=0 IBV=1e-10 BV=1e+30 CJO=0 M=0.5 VJ=1 )

V_Isense 0vNode K DC 0

* Interactive sense node
b1 lit 0 v = { if (i(V_Isense) < 0, 0, if( i(V_Isense) > 0.005, 1, { i(V_Isense) / 0.005 })) }

.ends

* LED2 subcircuit
.subckt LED_VIRTUAL_LED2 A K

dd1 A 0vNode ledDiodeModel
.model ledDiodeModel D( IS=1e-14 N=1 RS=0 IBV=1e-10 BV=1e+30 CJO=0 M=0.5 VJ=1 )

V_Isense 0vNode K DC 0

* Interactive sense node
b1 lit 0 v = { if (i(V_Isense) < 0, 0, if( i(V_Isense) > 0.005, 1, { i(V_Isense) / 0.005 })) }

.ends

* LED3 subcircuit
.subckt LED_VIRTUAL_LED3 A K

dd1 A 0vNode ledDiodeModel
.model ledDiodeModel D( IS=1e-14 N=1 RS=0 IBV=1e-10 BV=1e+30 CJO=0 M=0.5 VJ=1 )

V_Isense 0vNode K DC 0

* Interactive sense node
b1 lit 0 v = { if (i(V_Isense) < 0, 0, if( i(V_Isense) > 0.005, 1, { i(V_Isense) / 0.005 })) }

.ends

* clock subcircuit
.subckt Digital_Clock_clock out PARAMS: frequency=1000 duty=50 delay=0
a1 clk out
.model clk d_clock(frequency={frequency} duty={duty/100} delay={delay})
.ENDS


* --- Pin bridge models

.SUBCKT REAL_CUSTOM_ADC 1 2 PARAMS: lowV=0 maxLowV=0.8 unknownV=1.0 minHighV=2.0 highV=5.0 riseT=0 fallT=0
* Ideal Receiver Model 1 = input, 2 = A/D out
aADCin1 [2] [1] ADC
.MODEL ADC adc_bridge (in_low = {maxLowV} in_high = {minHighV})
.ENDS

.SUBCKT REAL_CUSTOM_DAC 1 2 PARAMS: lowV=0 maxLowV=0.8 unknownV=1.0 minHighV=2.0 highV=5.0 riseT=0 fallT=0
* Ideal Driver Model 1 = A/D out, 2 = input
aDACin1 [1] [2] aDAC
.MODEL aDAC dac_bridge (out_low = {lowV} out_high = {highV} out_undef = {unknownV} t_rise = {max(riseT,1e-9)} t_fall = {max(fallT,1e-9)})
.ENDS
VHDL Netlist

This is a text-based representation of a digital circuit.
The -- symbols indicates a comment.
Probes and analog components do not appear in VHDL netlists.

-- This is a VHDL representation of the -- digital circuit described in the schematic. -- If the circuit described is not valid or is incomplete, -- it may result in an invalid VHDL representation. library IEEE; use IEEE.STD_LOGIC_1164.ALL; USE WORK.ALL; entity top_design is Port ( ); end top_design; architecture BEHAVIORAL of top_design is signal \4\,\2\ : STD_LOGIC; begin end BEHAVIORAL;
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Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

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