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MCR08BT1GD1100Vrms60Hz120°V13VloadVsource5V60HzV22Vgate +REF1 -REF110kΩR1 V V V V
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ID:

ID:
x10
x0.1
Sheet:1
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triac
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fundamentals
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thyristor
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scr
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** Tiristor **
*
* Multisim Live SPICE netlist
*
*

* --- Circuit Topology ---

* Component: D1
xD1 3 2 1 MCR08MT1/ON_D1

* Component: R1
rR1 1 0 10000 VIRTUAL_RESISTANCE_R1

* Component: V1
vV1 3 0 dc 0 ac 1 0
+ distof1 0 0
+ distof2 0 0
+ sin ( 0 {100*1.414213562} 60 0 0 120 )

* Component: V2
vV2 2 1
+ pulse( 0 5 0 1e-9 1e-9
+ { 30 * 0.01 / 60 }
+ { 1/60 } )


* --- Circuit Models ---

* R1 model
.model VIRTUAL_RESISTANCE_R1 r( )


* --- Subcircuits ---

* D1 subcircuit
*$
.subckt MCR08MT1/ON_D1 anode gate cathode PARAMS:
**************************************
* Model Generated by EVAL LAB *
* July 23, 2003 *
* Copyright(c) On Semiconductor *
* All Rights Reserved *
*Commercial Use or Resale Restricted *
**************************************
*SCR
*MODEL FORMAT: PSpice
+ Vdrm=600v Vrrm=600v Idrm=10u
+ Ih=2.5ma dVdt=10e6
* Vgt must be greater than 0.65v
+ Igt=6.5ua Vgt=0.66v
+ Vtm=1.4v Itm=1.0
+ Ton=2u Toff=15u

* Where:
* Vdrm => Forward breakover voltage
* Vrrm => Reverse breakdown voltage
* Idrm => Peak blocking current
* Ih => Holding current
* dVdt => Critical value for dV/dt triggering
* Igt => Gate trigger current
* Vgt => Gate trigger voltage
* Vtm => On-state voltage
* Itm => On-state current
* Ton => Turn-on time
* Toff => Turn-off time

* Main conduction path
Scr anode anode0 control 0 Vswitch ; controlled switch
Dak1 anode0 anode2 Dakfwd OFF ; SCR is initially off
Dka cathode anode0 Dkarev OFF
VIak anode2 cathode ; current sensor

* dVdt Turn-on
Emon dvdt0 0 TABLE {v(anode,cathode)} (0 0) (2000 2000)
CdVdt dvdt0 dvdt1 100pfd ; displacement current
Rdlay dvdt1 dvdt2 1k
VdVdt dvdt2 cathode DC 0.0
EdVdt condvdt 0 TABLE {i(vdVdt)-100p*dVdt} (0 0 ) (.1m 10)
RdVdt condvdt 0 1meg

* Gate
Rseries gate gate1 {(Vgt-0.65)/Igt}
Rshunt gate1 gate2 {0.65/Igt}
Dgkf gate1 gate2 Dgk
VIgf gate2 cathode ; current sensor

* Gate Turn-on
Egate1 gate4 0 TABLE {i(Vigf)-0.95*Igt} (0 0) (1m 10)
Rgate1 gate4 0 1meg
Egon1 congate 0 TABLE {v(gate4)*v(anode,cathode)} (0 0) (10 10)
Rgon1 congate 0 1meg

* Main Turn-on
EItot Itot 0 TABLE {i(VIak)+5E-5*i(VIgf)/Igt} (0 0) (2000 2000)
RItot Itot 0 1meg
Eprod prod 0 TABLE {v(anode,cathode)*v(Itot)} (0 0) (1 1)
Rprod prod 0 1meg
Elin conmain 0 TABLE
+ {10*(v(prod) - (Vtm*Ih))/(Vtm*Ih)} (0 0) (2 10)
Rlin conmain 0 1meg

* Turn-on/Turn-off control
Eonoff contot 0 TABLE
+ {v(congate)+v(conmain)+v(condvdt)} (0 0) (10 10)

* Turn-on/Turn-off delays
Rton contot dlay1 825
Dton dlay1 control Delay
Rtoff contot dlay2 {290*Toff/Ton}
Dtoff control dlay2 Delay
Cton control 0 {Ton/454}

* Reverse breakdown
Dbreak anode break1 Dbreak
Dbreak2 cathode break1 Dseries

* Controlled switch model
.MODEL Vswitch vswitch
+ (Ron = {(Vtm-0.7)/Itm}, Roff = {Vdrm*Vdrm/(Vtm*Ih)},
+ Von = 5.0, Voff = 1.5)

* Diodes
.MODEL Dgk D (Is=1E-16 Cjo=50pf Rs=5)
.MODEL Dseries D (Is=1E-14)
.MODEL Delay D (Is=1E-12 Cjo=5pf Rs=0.01)
.MODEL Dkarev D (Is=1E-10 Cjo=5pf Rs=0.01)
.MODEL Dakfwd D (Is=4E-11 Cjo=5pf)
.MODEL Dbreak D (Ibv=1E-7 Bv={1.1*Vrrm} Cjo=5pf Rs=0.5)

* Allow the gate to float if required
Rfloat gate cathode 1e10

.ENDS
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-- This is a VHDL representation of the -- digital circuit described in the schematic. -- If the circuit described is not valid or is incomplete, -- it may result in an invalid VHDL representation. library IEEE; use IEEE.STD_LOGIC_1164.ALL; USE WORK.ALL; entity top_design is Port ( ); end top_design; architecture BEHAVIORAL of top_design is begin end BEHAVIORAL;
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