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D flip-flop from NAND gates Lab 07

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D flip-flop from NAND gates Lab 07
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D flip-flop created from NAND gates, using clock voltage as the data source. I recommend setting the Grapher time range from 0-5 seconds after running the simulation.

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Profile image for salman2255

Salman2255

1 Circuit

Date Created

3 years ago

Last Modified

3 years ago

Tags

  • digital
  • nand gate
  • flip-flop
  • digitaldigital electronics and logic design

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D flip-flop from NAND gates Lab 07

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