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VoutADJVin T1220Vrms50Hz0°V13N247D1345LM317HU281061000μFC110kΩ100%R17R41kΩ2C21000μFPR1 +REF1 -REF1R31kΩ V V
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ID:

ID:

x10
x0.1
Sheet:1
V
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1234567891011121314
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1234567891011121314
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Netlist
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SPICE
VHDL
SPICE Netlist

This is a text-based representation of the circuit.
The * symbol indicates a comment.
The + symbol indicates a continuation from the previous line.
Probes do not appear in netlists.

** Power Supply fixed 5V **
*
* Multisim Live SPICE netlist
*
*

* --- Circuit Topology ---

* Component: C1
cC1 6 0 0.001

* Component: C2
cC2 8 0 0.001

* Component: D1
xD1 5 4 6 0 D3N247_D1

* Component: R1
xR1 0 2 7 Potentiometer_R1 PARAMS: res=10000 posPercent=100

* Component: R3
rR3 6 0 1000 VIRTUAL_RESISTANCE_R3

* Component: R4
rR4 8 2 1000 VIRTUAL_RESISTANCE_R4

* Component: T1
xT1 1 3 5 4 1P1S_T1

* Component: U2
xU2 6 8 7 UPC317H_U2

* Component: V1
vV1 1 3 dc 0 ac 1 0
+ distof1 0 0
+ distof2 0 0
+ sin ( 0 {220*1.414213562} 50 0 0 0 )


* --- Circuit Models ---

* R3 model
.model VIRTUAL_RESISTANCE_R3 r( )

* R4 model
.model VIRTUAL_RESISTANCE_R4 r( )


* --- Subcircuits ---

* D1 subcircuit
.subckt D3N247_D1 AC1 AC2 + -
* EWB FWB Subckt Model
D1 AC2 + D3N247
D2 AC1 + D3N247
D3 - AC2 D3N247
D4 - AC1 D3N247
.MODEL D3N247 D (
+ IS = 1.001e-20
+ RS = 0.03767
+ CJO = 1e-12
+ VJ = 0.75
+ TT = 5e-09
+ M = 0.3333
+ BV = { 100 * 1.2 }
+ N = 0.9892
+ EG = 1.11
+ XTI = 3
+ KF = 0
+ AF = 1
+ FC = 0.5
+ IBV = 0.0001
+ TNOM = 27
+ )
.ENDS

* R1 subcircuit
.subckt Potentiometer_R1 T1 T2 T3 PARAMS: res=10k posPercent=50
.PARAM relPos = limit(posPercent * 0.01, 0.0000001, 0.9999999)
r1 T1 T2 {{res}*relPos}
r2 T2 T3 {{res} - {res}*relPos}
.ends

* T1 subcircuit
.SUBCKT 1P1S_T1 p1pos p1neg s1pos s1neg
.param PTurns = {10 * IF(PNegativePolarity < 0.5, 1, -1)}
.param PNegativePolarity = 0
.param STurns = {1 * IF(SNegativePolarity < 0.5, 1, -1)}
.param SNegativePolarity = 0
G1 p1pos p1neg value={-1/PTurns*(STurns*I(Es1))}
Es1 s1pos s1neg value={V(p1pos,p1neg)*STurns/PTurns}
.ENDS

* U2 subcircuit
.subckt UPC317H_U2 3 1 2
* Model Generated by MODPEX *
*Copyright(c) Symmetry Design Systems*
* All Rights Reserved *
* UNPUBLISHED LICENSED SOFTWARE *
* Contains Proprietary Information *
* Which is The Property of *
* SYMMETRY OR ITS LICENSORS *
*Commercial Use or Resale Restricted *
* by Symmetry License Agreement *
* Model generated on Sep 8, 97
* MODEL FORMAT: SPICE3
*Rev. Date: Dec. 20, 1994
*Positive Adjustable Regulator
*External Node Designations
*node 1: VREF (OUTPUT)
*node 2: Ground (Common)
*node 3: Line Voltage
ECCX 131 2 135 2 1.0
VXX 133 2 DC 0
FSET6 2 135 VSENS2 1
FPP 3 2 VXX 1.0
R_YY 31 2 1e6
R_XX 15 2 1e8
R_ZZ 36 2 1e6
R_QQ 65 2 1e8
RXX 1 2 1e8
VSENS1 10 1 DC 0
ISET 2 15 DC 1e-3
DON1 15 16 DMOD1
VSENS2 16 19 DC 0
DON2 15 17 DMOD1
EON2 18 2 3 2 1
FYY 3 2 VSENS1 1
DON3 15 27 DMOD1
VDROP3 28 27 DC 2
EON3 28 2 3 2 4
ELINE 13 42 66 2 1
FSET2 2 36 VSENS2 1
DSC1 36 35 DMOD1
RCL1 36 37 10
DSC2 37 38 DMOD1
ESCCON 38 39 30 2 1
VSCCON 39 40 DC 0
FSC 19 2 VSCCON 1
FSET3 2 31 VSENS2 1
DOV1 31 32 DMOD1
EOV1 32 2 3 1 1
DOV2 31 33 DMOD1
ISET4 2 30 DC 1e-3
ELOAD 41 2 77 2 -1
ERIPPLE 42 41 72 2 1
EREF 12 13 19 2 1
E3 52 2 3 2 1
CBYPS 54 2 0.001
VORB 54 60 DC 0
RB 60 2 1e3
RBR 72 2 1000
CBS2 52 71 1
RSTEP 77 2 1
FRB 2 65 VORB 1
DRB2 65 67 DMOD1
VXRB 67 68 DC -1
EXRB 68 2 1 2 1
DRB1 65 66 DMOD1
RB1 66 2 1000
.MODEL DMOD1 D
*-- DMOD1 DEFAULT PARAMETERS
*IS=1e-14 RS=0 N=1 TT=0 CJO=0
*VJ=1 M=0.5 EG=1.11 XTI=3 FC=0.5
*KF=0 AF=1 BV=inf IBV=1e-3 TNOM=27
EXX 132 131 3 131 0.006
RST6 135 2 10000
RIQX 133 132 RQIX 200000
.MODEL RQIX R TC1=-0.001
RSET 19 2 RSET 1250
.MODEL RSET R TC1=2e-05 TC2=9.8e-08
RS1 10 12 0.0033
VDROPX 18 17 1.26
HSENSE1 35 2 VSENS1 4.54545
RISC 30 2 RISC 10000
.MODEL RISC R TC1=-0.0006
ROV 34 2 35000
VOV 33 34 15
EOV2 2 40 34 2 0.181818
FIQD 3 2 VSENS1 1e-07
RY 52 54 8e+06
RA 72 73 2177.21
RYR 71 72 315228
CRA 52 73 1.67142e-09
HSTEP 76 2 VSENS1 0.2
CSTEP 76 77 1e-05
.ENDS upc317h

VHDL Netlist

This is a text-based representation of a digital circuit.
The -- symbols indicates a comment.
Probes and analog components do not appear in VHDL netlists.

-- This is a VHDL representation of the -- digital circuit described in the schematic. -- If the circuit described is not valid or is incomplete, -- it may result in an invalid VHDL representation. library IEEE; use IEEE.STD_LOGIC_1164.ALL; USE WORK.ALL; entity top_design is Port ( ); end top_design; architecture BEHAVIORAL of top_design is begin end BEHAVIORAL;
Errors and Warnings

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Power Supply fixed 5V
Schematic

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Name

Start time

s

End time

s

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Mode

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

V

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

V

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

V

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

V

Output high voltage.

Minimum output voltage level to produce a high signal.

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Height

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Grid

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