*Digital to Analog Converter

Waiting for data

Signal	Value
Signal	Value

Cursor 1	Cursor 2	∆X	1/∆X	∆Y	∆Y (Phase)

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

ID:

x10

x0.1

Sheet:1

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resistors

dac/adc

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SPICE Netlist

This is a text-based representation of the circuit.
The * symbol indicates a comment.
The + symbol indicates a continuation from the previous line.
Probes do not appear in netlists.

** Digital to Analog Converter - DAC **
*
* Multisim Live SPICE netlist
*
*

* --- Circuit Topology ---

* Component: D1
aD1 9 8 ZENER_VIRTUAL_D1

* Component: K1
xK1 K1_NC_L1 K1_NC_L2 K1_NC_C1 K1_NC_C2 8 Combination_Relay_K1 PARAMS: coil_inductance=0.001 coil_resistance=1 on_current=0.05 off_current=0.025

* Component: LED1
xLED1 D3 4 LED_VIRTUAL_LED1

* Component: LED2
xLED2 D1 5 LED_VIRTUAL_LED2

* Component: LED3
xLED3 D1 6 LED_VIRTUAL_LED3

* Component: LED4
xLED4 D0 7 LED_VIRTUAL_LED4

* Component: Q1
qQ1 7 9 7 NPN_Q1 AREA=1

* Component: R1
rR1 D0 1 200 VIRTUAL_RESISTANCE_R1

* Component: R10
rR10 5 0 200 VIRTUAL_RESISTANCE_R10

* Component: R11
rR11 6 0 200 VIRTUAL_RESISTANCE_R11

* Component: R12
rR12 7 0 200 VIRTUAL_RESISTANCE_R12

* Component: R2
rR2 0 1 200 VIRTUAL_RESISTANCE_R2

* Component: R3
rR3 D1 2 200 VIRTUAL_RESISTANCE_R3

* Component: R4
rR4 1 2 100 VIRTUAL_RESISTANCE_R4

* Component: R5
rR5 D1 3 200 VIRTUAL_RESISTANCE_R5

* Component: R6
rR6 2 3 100 VIRTUAL_RESISTANCE_R6

* Component: R7
rR7 D3 Analog_Out 200 VIRTUAL_RESISTANCE_R7

* Component: R8
rR8 3 Analog_Out 100 VIRTUAL_RESISTANCE_R8

* Component: R9
rR9 4 0 2e-12 VIRTUAL_RESISTANCE_R9

* Component: U1
aU1 [bridgeU1!A U1_NC_B U1_NC_C] bridgeU1!Y Digital_AND3_U1

xbridgeU1!A bridgeU1!A 0 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU1!Y bridgeU1!Y 0 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: V1
vV1 D0 0 dc 0
+ pwlrepeat
+ 0 0
+ 0.0009 0
+ 0.001 2
+ 0.0019 2
+ 0.002 0

* Component: V5
vV5 D1 0 dc 0
+ pwlrepeat
+ 0 0
+ 0.0019 0
+ 0.002 2
+ 0.0039 2
+ 0.004 0

* Component: V6
vV6 D1 0 dc 0
+ pwlrepeat
+ 0 0
+ 0.0039 0
+ 0.004 2
+ 0.0079 2
+ 0.008 0

* Component: V7
vV7 D3 0 dc 0
+ pwlrepeat
+ 0 0
+ 0.0079 0
+ 0.008 2
+ 0.0159 2
+ 0.016 0

* Component: X1
xX1 Analog_Out X1_NC_2 VIR_LAMP_X1

* --- Circuit Models ---

* D1 model
.model ZENER_VIRTUAL_D1 ZENER ( v_breakdown=5 i_breakdown=0.02 i_sat=1e-12 n_forward=1 )

* Q1 model
.model NPN_Q1 NPN( Level=1
+ IS=1e-16 BF=100 NF=1 VAF=1e+30
+ IKF=1e+30 ISE=0 NE=1.5 BR=1 NR=1 VAR=1e+30 IKR=1e+30 ISC=0 NC=2 RB=0
+ IRB=1e+30 RE=0 RC=0 CJE=0 VJE=0.75 MJE=0.33 TF=0 XTF=0 VTF=1e+30
+ ITF=0 PTF=0 CJC=0 VJC=0.75 MJC=0.33 XCJC=1 TR=0 CJS=0 VJS=0.75 MJS=0
+ XTB=0 EG=1.11 XTI=3 KF=0 AF=1 FC=0.5 NS=1
+ XCJC2=1 XCJS=1 TRB1=0 TRB2=0 TRC1=0 TRC2=0 TRE1=0 TRE2=0 TRM1=0 TRM2=0
+ CN=2.2 D=0.52 GAMMA=1e-11 QCO=0 QUASIMOD=0 RCO=0 VG=1.206 VO=10
+
+ )

* R1 model
.model VIRTUAL_RESISTANCE_R1 r( )

* R10 model
.model VIRTUAL_RESISTANCE_R10 r( )

* R11 model
.model VIRTUAL_RESISTANCE_R11 r( )

* R12 model
.model VIRTUAL_RESISTANCE_R12 r( )

* R2 model
.model VIRTUAL_RESISTANCE_R2 r( )

* R3 model
.model VIRTUAL_RESISTANCE_R3 r( )

* R4 model
.model VIRTUAL_RESISTANCE_R4 r( )

* R5 model
.model VIRTUAL_RESISTANCE_R5 r( )

* R6 model
.model VIRTUAL_RESISTANCE_R6 r( )

* R7 model
.model VIRTUAL_RESISTANCE_R7 r( )

* R8 model
.model VIRTUAL_RESISTANCE_R8 r( )

* R9 model
.model VIRTUAL_RESISTANCE_R9 r( )

* U1 model
.model Digital_AND3_U1 d_and (rise_delay=1e-9 fall_delay=1e-9)

* --- Subcircuits ---

* K1 subcircuit
.SUBCKT Combination_Relay_K1 1 2 3 4 5 PARAMS: coil_inductance=1m coil_resistance=1 on_current=50m off_current=25m
L1 1 6 coil_inductance
RL 6 7 coil_resistance
Vsens 7 2 DC 0
W0 3 4 Vsens NO_contact
W1 4 5 Vsens NC_contact
.MODEL NO_contact CSW (
+ IT={off_current+(on_current-off_current)/2}
+ IH={(on_current-off_current)/2}
+ Ron=1e-8 Roff=1e30)
.MODEL NC_contact CSW (
+ IT={off_current+(on_current-off_current)/2}
+ IH={(on_current-off_current)/2}
+ Ron=1e30 Roff=1e-8)
.ENDS

* LED1 subcircuit
.subckt LED_VIRTUAL_LED1 A K

dd1 A 0vNode ledDiodeModel
.model ledDiodeModel D( IS=1e-14 N=1 RS=0 IBV=1e-10 BV=1e+30 CJO=0 M=0.5 VJ=1 )

V_Isense 0vNode K DC 0

* Interactive sense node
b1 lit 0 v = { if (i(V_Isense) < 0, 0, if( i(V_Isense) > 0.005, 1, { i(V_Isense) / 0.005 })) }

.ends

* LED2 subcircuit
.subckt LED_VIRTUAL_LED2 A K

dd1 A 0vNode ledDiodeModel
.model ledDiodeModel D( IS=1e-14 N=1 RS=0 IBV=1e-10 BV=1e+30 CJO=0 M=0.5 VJ=1 )

V_Isense 0vNode K DC 0

* Interactive sense node
b1 lit 0 v = { if (i(V_Isense) < 0, 0, if( i(V_Isense) > 0.005, 1, { i(V_Isense) / 0.005 })) }

.ends

* LED3 subcircuit
.subckt LED_VIRTUAL_LED3 A K

dd1 A 0vNode ledDiodeModel
.model ledDiodeModel D( IS=1e-14 N=1 RS=0 IBV=1e-10 BV=1e+30 CJO=0 M=0.5 VJ=1 )

V_Isense 0vNode K DC 0

* Interactive sense node
b1 lit 0 v = { if (i(V_Isense) < 0, 0, if( i(V_Isense) > 0.005, 1, { i(V_Isense) / 0.005 })) }

.ends

* LED4 subcircuit
.subckt LED_VIRTUAL_LED4 A K

dd1 A 0vNode ledDiodeModel
.model ledDiodeModel D( IS=1e-14 N=1 RS=0 IBV=1e-10 BV=1e+30 CJO=0 M=0.5 VJ=1 )

V_Isense 0vNode K DC 0

* Interactive sense node
b1 lit 0 v = { if (i(V_Isense) < 0, 0, if( i(V_Isense) > 0.005, 1, { i(V_Isense) / 0.005 })) }

.ends

* X1 subcircuit
.subckt VIR_LAMP_X1 port1 port2

** resistance of the lamp when conducting current
.param lampResistance = {12^2/10}

** resistance of the lamp after burning out
.param blownResistance = 10e6

** blown signal appears on node blown. 5V = blown, 0 = not
Rdummy blown 0 1000000

** Constant digital high to feed as input to latch
aU2 dU1.DATA d_constsource_U2
.model d_constsource_U2 d_constsource(state=1)

**D-latch to latch state
aU1 dU1.DATA
+ dU1.EN
+ U1_OPEN_SET
+ U1_OPEN_RESET
+ dU1.Q
+ U1_OPEN_notQ D_LATCH

** Output of latch onto node `blown` through DAC
xU1.Q dU1.Q blown TIL_DRV

** Input node `trigger` to latch ENABLE through ADC
xU1.CLK trigger dU1.EN TIL_RCV

** If over blown voltage, trigger DLATCH U1 enable
E2 trigger 0 Value = { if(abs(V(port1, port2)) > 15 & Time > 0, 5, 0) }

** Modelling LIT and HOT states
blit lit 0 v={if(abs(V(port1, port2)) <= 12, {abs(V(port1, port2)) / 12}, 1)}
bhot hot 0 v={abs(V(port1, port2)) >= 12}

** Current sensor
V_Isense port1 lampSense 0

** model of the lamp as a G source so we can change the resistance on the fly
G_Lamp lampSense port2 value = { if( V(blown) < 2.5, V(port1, port2) / lampResistance, V(port1, port2) / blownResistance )}

.subckt TIL_DRV 1 2
* TIL Driver Model 1= D/A input, 2 = out
aDACin1 [1] [2] aDAC
.model aDAC dac_bridge (out_low = 0 out_high = 5 out_undef = 2.5)
.ends

.subckt TIL_RCV 1 2
* TIL Receiver Model 1 = input, 2 = A/D out
aADCin1 [1] [2] ADC
.model ADC adc_bridge (in_low = 2.5 in_high = 2.5)
.ends

.model D_LATCH d_dlatch (data_delay = 1n enable_delay = 1n
+ set_delay = 1n reset_delay = 1n
+ ic = 0 rise_delay = 1n fall_delay = 1n)

.ends

* --- Pin bridge models

.SUBCKT REAL_CUSTOM_ADC 1 2 PARAMS: lowV=0 maxLowV=0.8 unknownV=1.0 minHighV=2.0 highV=5.0 riseT=0 fallT=0
* Ideal Receiver Model 1 = input, 2 = A/D out
aADCin1 [2] [1] ADC
.MODEL ADC adc_bridge (in_low = {maxLowV} in_high = {minHighV})
.ENDS

.SUBCKT REAL_CUSTOM_DAC 1 2 PARAMS: lowV=0 maxLowV=0.8 unknownV=1.0 minHighV=2.0 highV=5.0 riseT=0 fallT=0
* Ideal Driver Model 1 = A/D out, 2 = input
aDACin1 [1] [2] aDAC
.MODEL aDAC dac_bridge (out_low = {lowV} out_high = {highV} out_undef = {unknownV} t_rise = {max(riseT,1e-9)} t_fall = {max(fallT,1e-9)})
.ENDS

VHDL Netlist

This is a text-based representation of a digital circuit.
The -- symbols indicates a comment.
Probes and analog components do not appear in VHDL netlists.

-- This is a VHDL representation of the -- digital circuit described in the schematic. -- If the circuit described is not valid or is incomplete, -- it may result in an invalid VHDL representation. library IEEE; use IEEE.STD_LOGIC_1164.ALL; USE WORK.ALL; entity top_design is Port ( ); end top_design; architecture BEHAVIORAL of top_design is begin end BEHAVIORAL;

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Type

Rise time

Time it takes for signal to transition from low to high.

With non-zero rise time, the signal converts to an analog signal from a digital signal.

Fall time

Time it takes for signal to transition from high to low.

With non-zero fall time, the signal converts to an analog signal from a digital signal.

Use document settings

Use logic levels settings from Document tab.

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

Type Probe

Select desired function.

Function

Use document settings

Use logic levels settings from Document tab.

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

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Name Digital to Analog Converter - DAC

Type Schematic

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Name

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RELTOL

Relative error tolerance. A simulation wide accuracy control used to establish convergence.

VNTOL

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ABSTOL

Absolute current error tolerance. Defines the minimum value for current where it may still be considered accurate.

ITL1

DC iteration limit. Number of iterative passes done on DC circuit equations in attempt to reach convergence in simulation.

ITL4

Upper iteration limit. Number of iterative passes done per time point, on Transient circuit equations in attempt to reach convergence in simulation.

Integration method. The numerical integration method used in transient analysis.

Temp

℃

Operating temperature. The temperature at which the entire circuit will be simulated.

Insert shunt resistance

Inserts a resistance of RSHUNT from every analog node to ground. Will aid in convergence, but alter the behavior of the circuit.

RSHUNT

Shunt resistance. This eliminates singular matrix errors that result from a lack of a DC path to ground.

Reset to default

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

Width

Sheet width in grid squares.

Height

Sheet height in grid squares.

Grid

Toggles grid display.

Net Labels

Toggles all net labels.

Component Labels

Toggles all component labels.

Digital to Analog Converter - DAC