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J-K FLIP FLOP

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J-K FLIP FLOP
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D flip-flop created from NAND gates, using clock voltage as the data source. I recommend setting the Grapher time range from 0-5 seconds after running the simulation.

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Profile image for kritikasrivastava

kritikasrivastava

13 Circuits

Date Created

3 years, 1 month ago

Last Modified

3 years, 1 month ago

Tags

  • digital
  • nand gate
  • flip-flop

Circuit Copied From

D flip-flop from NAND gates

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