Copy of F=AB'C'+BC'D'

This circuit determines whether the majority of the input signals are logic 1s or logic 0s. If the majority of the input signals consist of 1s the output is set to logic 1 otherwise it will be at logic 0. This particular circuit is the simplest majority voting logic circuit, having only three inputs. The circuit simply checks if any two combination of the input signals are all 1s. This is done by using three two-input AND gates with the outputs applied to a three-input OR gate. A notable application of this circuit is in generation of the carry output in full-adders.