*ЛАба 7

Waiting for data

Signal	Value
Signal	Value

Cursor 1	Cursor 2	∆X	1/∆X	∆Y	∆Y (Phase)

ID:

x10

x0.1

Sheet:1

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EPC2014

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BSP250

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Sensors...

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rad to deg

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Linear regulators...

LM1084-3.3

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MC34063A

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IR2010

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Digital

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Buffer

Inverter

Flip-Flops & Latches

D Flip-Flop

JK Flip-Flop

SR Flip-Flop

T Flip-Flop

D Latch

SR Latch

BCD to 7-Segment Decoders

74LS47N

74LS48N

Binary Counters

74LS93N

74LS193N

74LS163N

Mux/Demux

74LS139D

MUX2:1

Adders

74LS183D

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SPICE

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SPICE Netlist

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** ЛАба 7 **
*
* Multisim Live SPICE netlist
*
*

* --- Circuit Topology ---

* Component: FF0
xFF0 11 11 2 12 13 bridgeFF0!Q FF0_NC_~Q Digital_JKFlipFlop_FF0 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

xbridgeFF0!Q bridgeFF0!Q 4 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: FF1
xFF1 11 11 bridgeFF1!CLK 12 13 bridgeFF1!Q FF1_NC_~Q Digital_JKFlipFlop_FF1 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

xbridgeFF1!CLK bridgeFF1!CLK 4 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeFF1!Q bridgeFF1!Q 5 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: FF10
xFF10 11 11 bridgeFF10!CLK 12 13 bridgeFF10!Q FF10_NC_~Q Digital_JKFlipFlop_FF10 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

xbridgeFF10!CLK bridgeFF10!CLK 18 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeFF10!Q bridgeFF10!Q 19 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: FF11
xFF11 11 11 bridgeFF11!CLK 12 13 bridgeFF11!Q FF11_NC_~Q Digital_JKFlipFlop_FF11 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

xbridgeFF11!CLK bridgeFF11!CLK 17 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeFF11!Q bridgeFF11!Q 18 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: FF12
xFF12 11 11 bridgeFF12!CLK 12 13 bridgeFF12!Q FF12_NC_~Q Digital_JKFlipFlop_FF12 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

xbridgeFF12!CLK bridgeFF12!CLK 16 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeFF12!Q bridgeFF12!Q 17 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: FF13
xFF13 11 11 bridgeFF13!CLK 12 13 bridgeFF13!Q FF13_NC_~Q Digital_JKFlipFlop_FF13 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

xbridgeFF13!CLK bridgeFF13!CLK 15 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeFF13!Q bridgeFF13!Q 16 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: FF14
xFF14 11 11 bridgeFF14!CLK 12 13 bridgeFF14!Q FF14_NC_~Q Digital_JKFlipFlop_FF14 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

xbridgeFF14!CLK bridgeFF14!CLK 14 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeFF14!Q bridgeFF14!Q 15 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: FF15
xFF15 11 11 1 12 13 bridgeFF15!Q FF15_NC_~Q Digital_JKFlipFlop_FF15 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

xbridgeFF15!Q bridgeFF15!Q 14 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: FF2
xFF2 11 11 bridgeFF2!CLK 12 13 bridgeFF2!Q FF2_NC_~Q Digital_JKFlipFlop_FF2 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

xbridgeFF2!CLK bridgeFF2!CLK 5 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeFF2!Q bridgeFF2!Q 6 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: FF3
xFF3 11 11 bridgeFF3!CLK 12 13 bridgeFF3!Q FF3_NC_~Q Digital_JKFlipFlop_FF3 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

xbridgeFF3!CLK bridgeFF3!CLK 6 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeFF3!Q bridgeFF3!Q 7 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: FF4
xFF4 11 11 bridgeFF4!CLK 12 13 bridgeFF4!Q FF4_NC_~Q Digital_JKFlipFlop_FF4 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

xbridgeFF4!CLK bridgeFF4!CLK 7 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeFF4!Q bridgeFF4!Q 8 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: FF5
xFF5 11 11 bridgeFF5!CLK 12 13 bridgeFF5!Q FF5_NC_~Q Digital_JKFlipFlop_FF5 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

xbridgeFF5!CLK bridgeFF5!CLK 8 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeFF5!Q bridgeFF5!Q 9 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: FF6
xFF6 11 11 bridgeFF6!CLK 12 13 bridgeFF6!Q FF6_NC_~Q Digital_JKFlipFlop_FF6 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

xbridgeFF6!CLK bridgeFF6!CLK 9 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeFF6!Q bridgeFF6!Q 10 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: FF7
xFF7 11 11 bridgeFF7!CLK 12 13 1 FF7_NC_~Q Digital_JKFlipFlop_FF7 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

xbridgeFF7!CLK bridgeFF7!CLK 10 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: FF8
xFF8 11 11 bridgeFF8!CLK 12 13 FF8_NC_Q FF8_NC_~Q Digital_JKFlipFlop_FF8 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

xbridgeFF8!CLK bridgeFF8!CLK 20 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: FF9
xFF9 11 11 bridgeFF9!CLK 12 13 bridgeFF9!Q FF9_NC_~Q Digital_JKFlipFlop_FF9 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

xbridgeFF9!CLK bridgeFF9!CLK 19 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeFF9!Q bridgeFF9!Q 20 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: R1
rR1 4 0 100000 VIRTUAL_RESISTANCE_R1

* Component: R10
rR10 18 0 100000 VIRTUAL_RESISTANCE_R10

* Component: R11
rR11 17 0 100000 VIRTUAL_RESISTANCE_R11

* Component: R12
rR12 16 0 100000 VIRTUAL_RESISTANCE_R12

* Component: R13
rR13 15 0 100000 VIRTUAL_RESISTANCE_R13

* Component: R14
rR14 14 0 100000 VIRTUAL_RESISTANCE_R14

* Component: R2
rR2 5 0 100000 VIRTUAL_RESISTANCE_R2

* Component: R3
rR3 6 0 100000 VIRTUAL_RESISTANCE_R3

* Component: R4
rR4 7 0 100000 VIRTUAL_RESISTANCE_R4

* Component: R5
rR5 8 0 100000 VIRTUAL_RESISTANCE_R5

* Component: R6
rR6 9 0 100000 VIRTUAL_RESISTANCE_R6

* Component: R7
rR7 10 0 100000 VIRTUAL_RESISTANCE_R7

* Component: R8
rR8 20 0 100000 VIRTUAL_RESISTANCE_R8

* Component: R9
rR9 19 0 100000 VIRTUAL_RESISTANCE_R9

* Component: Reset
aReset 13 Digital_Source_Reset

* Component: Set
aSet 12 Digital_Source_Set

* Component: U
aU 11 Digital_Source_U

* Component: U1
aU1 bridgeU1!A 2 Digital_Inverter_U1

xbridgeU1!A bridgeU1!A 3 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: V1
vV1 3 0 ac 1 0
+ distof1 0 0
+ distof2 0 0
+ pulse(0 5 0 1e-9 1e-9 0.1 1)

* --- Circuit Models ---

* R1 model
.model VIRTUAL_RESISTANCE_R1 r( )

* R10 model
.model VIRTUAL_RESISTANCE_R10 r( )

* R11 model
.model VIRTUAL_RESISTANCE_R11 r( )

* R12 model
.model VIRTUAL_RESISTANCE_R12 r( )

* R13 model
.model VIRTUAL_RESISTANCE_R13 r( )

* R14 model
.model VIRTUAL_RESISTANCE_R14 r( )

* R2 model
.model VIRTUAL_RESISTANCE_R2 r( )

* R3 model
.model VIRTUAL_RESISTANCE_R3 r( )

* R4 model
.model VIRTUAL_RESISTANCE_R4 r( )

* R5 model
.model VIRTUAL_RESISTANCE_R5 r( )

* R6 model
.model VIRTUAL_RESISTANCE_R6 r( )

* R7 model
.model VIRTUAL_RESISTANCE_R7 r( )

* R8 model
.model VIRTUAL_RESISTANCE_R8 r( )

* R9 model
.model VIRTUAL_RESISTANCE_R9 r( )

* Reset model
.model Digital_Source_Reset d_constsource(State=0)

* Set model
.model Digital_Source_Set d_constsource(State=1)

* U model
.model Digital_Source_U d_constsource(State=0)

* U1 model
.model Digital_Inverter_U1 d_inverter (rise_delay=1e-9 fall_delay=1e-9)

* --- Subcircuits ---

* FF0 subcircuit
.subckt Digital_JKFlipFlop_FF0 1 2 3 4 5 6 7 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n

aDG1 neg_SR initSR
aDG2 neg_clk initCLK
A1 [4 neg_SR] set xorset
A2 [3 neg_clk] clk xorclk
A3 [5 neg_SR] reset xorreset
A4 1 2 clk set reset 6 7 JK_FF
**MODELS USED*
.model initCLK d_constsource(State={Negative_Edge_Clock})
.model initSR d_constsource(State={Negative_SET_RESET})
.model xorset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorclk d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorreset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.MODEL JK_FF d_jkff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS

* FF1 subcircuit
.subckt Digital_JKFlipFlop_FF1 1 2 3 4 5 6 7 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n

aDG1 neg_SR initSR
aDG2 neg_clk initCLK
A1 [4 neg_SR] set xorset
A2 [3 neg_clk] clk xorclk
A3 [5 neg_SR] reset xorreset
A4 1 2 clk set reset 6 7 JK_FF
**MODELS USED*
.model initCLK d_constsource(State={Negative_Edge_Clock})
.model initSR d_constsource(State={Negative_SET_RESET})
.model xorset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorclk d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorreset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.MODEL JK_FF d_jkff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS

* FF10 subcircuit
.subckt Digital_JKFlipFlop_FF10 1 2 3 4 5 6 7 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n

aDG1 neg_SR initSR
aDG2 neg_clk initCLK
A1 [4 neg_SR] set xorset
A2 [3 neg_clk] clk xorclk
A3 [5 neg_SR] reset xorreset
A4 1 2 clk set reset 6 7 JK_FF
**MODELS USED*
.model initCLK d_constsource(State={Negative_Edge_Clock})
.model initSR d_constsource(State={Negative_SET_RESET})
.model xorset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorclk d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorreset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.MODEL JK_FF d_jkff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS

* FF11 subcircuit
.subckt Digital_JKFlipFlop_FF11 1 2 3 4 5 6 7 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n

aDG1 neg_SR initSR
aDG2 neg_clk initCLK
A1 [4 neg_SR] set xorset
A2 [3 neg_clk] clk xorclk
A3 [5 neg_SR] reset xorreset
A4 1 2 clk set reset 6 7 JK_FF
**MODELS USED*
.model initCLK d_constsource(State={Negative_Edge_Clock})
.model initSR d_constsource(State={Negative_SET_RESET})
.model xorset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorclk d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorreset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.MODEL JK_FF d_jkff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS

* FF12 subcircuit
.subckt Digital_JKFlipFlop_FF12 1 2 3 4 5 6 7 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n

aDG1 neg_SR initSR
aDG2 neg_clk initCLK
A1 [4 neg_SR] set xorset
A2 [3 neg_clk] clk xorclk
A3 [5 neg_SR] reset xorreset
A4 1 2 clk set reset 6 7 JK_FF
**MODELS USED*
.model initCLK d_constsource(State={Negative_Edge_Clock})
.model initSR d_constsource(State={Negative_SET_RESET})
.model xorset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorclk d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorreset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.MODEL JK_FF d_jkff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS

* FF13 subcircuit
.subckt Digital_JKFlipFlop_FF13 1 2 3 4 5 6 7 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n

aDG1 neg_SR initSR
aDG2 neg_clk initCLK
A1 [4 neg_SR] set xorset
A2 [3 neg_clk] clk xorclk
A3 [5 neg_SR] reset xorreset
A4 1 2 clk set reset 6 7 JK_FF
**MODELS USED*
.model initCLK d_constsource(State={Negative_Edge_Clock})
.model initSR d_constsource(State={Negative_SET_RESET})
.model xorset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorclk d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorreset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.MODEL JK_FF d_jkff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS

* FF14 subcircuit
.subckt Digital_JKFlipFlop_FF14 1 2 3 4 5 6 7 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n

aDG1 neg_SR initSR
aDG2 neg_clk initCLK
A1 [4 neg_SR] set xorset
A2 [3 neg_clk] clk xorclk
A3 [5 neg_SR] reset xorreset
A4 1 2 clk set reset 6 7 JK_FF
**MODELS USED*
.model initCLK d_constsource(State={Negative_Edge_Clock})
.model initSR d_constsource(State={Negative_SET_RESET})
.model xorset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorclk d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorreset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.MODEL JK_FF d_jkff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS

* FF15 subcircuit
.subckt Digital_JKFlipFlop_FF15 1 2 3 4 5 6 7 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n

aDG1 neg_SR initSR
aDG2 neg_clk initCLK
A1 [4 neg_SR] set xorset
A2 [3 neg_clk] clk xorclk
A3 [5 neg_SR] reset xorreset
A4 1 2 clk set reset 6 7 JK_FF
**MODELS USED*
.model initCLK d_constsource(State={Negative_Edge_Clock})
.model initSR d_constsource(State={Negative_SET_RESET})
.model xorset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorclk d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorreset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.MODEL JK_FF d_jkff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS

* FF2 subcircuit
.subckt Digital_JKFlipFlop_FF2 1 2 3 4 5 6 7 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n

aDG1 neg_SR initSR
aDG2 neg_clk initCLK
A1 [4 neg_SR] set xorset
A2 [3 neg_clk] clk xorclk
A3 [5 neg_SR] reset xorreset
A4 1 2 clk set reset 6 7 JK_FF
**MODELS USED*
.model initCLK d_constsource(State={Negative_Edge_Clock})
.model initSR d_constsource(State={Negative_SET_RESET})
.model xorset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorclk d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorreset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.MODEL JK_FF d_jkff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS

* FF3 subcircuit
.subckt Digital_JKFlipFlop_FF3 1 2 3 4 5 6 7 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n

aDG1 neg_SR initSR
aDG2 neg_clk initCLK
A1 [4 neg_SR] set xorset
A2 [3 neg_clk] clk xorclk
A3 [5 neg_SR] reset xorreset
A4 1 2 clk set reset 6 7 JK_FF
**MODELS USED*
.model initCLK d_constsource(State={Negative_Edge_Clock})
.model initSR d_constsource(State={Negative_SET_RESET})
.model xorset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorclk d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorreset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.MODEL JK_FF d_jkff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS

* FF4 subcircuit
.subckt Digital_JKFlipFlop_FF4 1 2 3 4 5 6 7 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n

aDG1 neg_SR initSR
aDG2 neg_clk initCLK
A1 [4 neg_SR] set xorset
A2 [3 neg_clk] clk xorclk
A3 [5 neg_SR] reset xorreset
A4 1 2 clk set reset 6 7 JK_FF
**MODELS USED*
.model initCLK d_constsource(State={Negative_Edge_Clock})
.model initSR d_constsource(State={Negative_SET_RESET})
.model xorset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorclk d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorreset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.MODEL JK_FF d_jkff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS

* FF5 subcircuit
.subckt Digital_JKFlipFlop_FF5 1 2 3 4 5 6 7 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n

aDG1 neg_SR initSR
aDG2 neg_clk initCLK
A1 [4 neg_SR] set xorset
A2 [3 neg_clk] clk xorclk
A3 [5 neg_SR] reset xorreset
A4 1 2 clk set reset 6 7 JK_FF
**MODELS USED*
.model initCLK d_constsource(State={Negative_Edge_Clock})
.model initSR d_constsource(State={Negative_SET_RESET})
.model xorset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorclk d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorreset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.MODEL JK_FF d_jkff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS

* FF6 subcircuit
.subckt Digital_JKFlipFlop_FF6 1 2 3 4 5 6 7 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n

aDG1 neg_SR initSR
aDG2 neg_clk initCLK
A1 [4 neg_SR] set xorset
A2 [3 neg_clk] clk xorclk
A3 [5 neg_SR] reset xorreset
A4 1 2 clk set reset 6 7 JK_FF
**MODELS USED*
.model initCLK d_constsource(State={Negative_Edge_Clock})
.model initSR d_constsource(State={Negative_SET_RESET})
.model xorset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorclk d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorreset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.MODEL JK_FF d_jkff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS

* FF7 subcircuit
.subckt Digital_JKFlipFlop_FF7 1 2 3 4 5 6 7 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n

aDG1 neg_SR initSR
aDG2 neg_clk initCLK
A1 [4 neg_SR] set xorset
A2 [3 neg_clk] clk xorclk
A3 [5 neg_SR] reset xorreset
A4 1 2 clk set reset 6 7 JK_FF
**MODELS USED*
.model initCLK d_constsource(State={Negative_Edge_Clock})
.model initSR d_constsource(State={Negative_SET_RESET})
.model xorset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorclk d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorreset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.MODEL JK_FF d_jkff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS

* FF8 subcircuit
.subckt Digital_JKFlipFlop_FF8 1 2 3 4 5 6 7 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n

aDG1 neg_SR initSR
aDG2 neg_clk initCLK
A1 [4 neg_SR] set xorset
A2 [3 neg_clk] clk xorclk
A3 [5 neg_SR] reset xorreset
A4 1 2 clk set reset 6 7 JK_FF
**MODELS USED*
.model initCLK d_constsource(State={Negative_Edge_Clock})
.model initSR d_constsource(State={Negative_SET_RESET})
.model xorset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorclk d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorreset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.MODEL JK_FF d_jkff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS

* FF9 subcircuit
.subckt Digital_JKFlipFlop_FF9 1 2 3 4 5 6 7 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n

aDG1 neg_SR initSR
aDG2 neg_clk initCLK
A1 [4 neg_SR] set xorset
A2 [3 neg_clk] clk xorclk
A3 [5 neg_SR] reset xorreset
A4 1 2 clk set reset 6 7 JK_FF
**MODELS USED*
.model initCLK d_constsource(State={Negative_Edge_Clock})
.model initSR d_constsource(State={Negative_SET_RESET})
.model xorset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorclk d_xor(rise_delay=1e-9 fall_delay=1e-9)
.model xorreset d_xor(rise_delay=1e-9 fall_delay=1e-9)
.MODEL JK_FF d_jkff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS

* --- Pin bridge models

.SUBCKT REAL_CUSTOM_DAC 1 2 PARAMS: lowV=0 maxLowV=0.8 unknownV=1.0 minHighV=2.0 highV=5.0 riseT=0 fallT=0
* Ideal Driver Model 1 = A/D out, 2 = input
aDACin1 [1] [2] aDAC
.MODEL aDAC dac_bridge (out_low = {lowV} out_high = {highV} out_undef = {unknownV} t_rise = {max(riseT,1e-9)} t_fall = {max(fallT,1e-9)})
.ENDS

.SUBCKT REAL_CUSTOM_ADC 1 2 PARAMS: lowV=0 maxLowV=0.8 unknownV=1.0 minHighV=2.0 highV=5.0 riseT=0 fallT=0
* Ideal Receiver Model 1 = input, 2 = A/D out
aADCin1 [2] [1] ADC
.MODEL ADC adc_bridge (in_low = {maxLowV} in_high = {minHighV})
.ENDS

VHDL Netlist

This is a text-based representation of a digital circuit.
The -- symbols indicates a comment.
Probes and analog components do not appear in VHDL netlists.

-- This is a VHDL representation of the -- digital circuit described in the schematic. -- If the circuit described is not valid or is incomplete, -- it may result in an invalid VHDL representation. library IEEE; use IEEE.STD_LOGIC_1164.ALL; USE WORK.ALL; entity top_design is Port ( ); end top_design; architecture BEHAVIORAL of top_design is signal \2\,\1\ : STD_LOGIC; begin end BEHAVIORAL;

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