Browser not supported

✕
Go back

Tier limit reached

✕

updown counter

0
Favorite
3
copy
Copy
266
Views
Open Circuit
updown counter
Social Share
Embed circuit
Embed linked image

Circuit Description

Graph image for updown counter

Circuit Graph

Synchronous Counter Design a 3-bit synchronous counter with the sequence below by using JK flip flops. 1 5  3  7  4 0 2  6  ... Apply the clock pulses and observe the output. Verify your design with output waveform simulation

There are currently no comments

Profile image for aa9896

RA2111003011368

aa9896
Profile image for AryanAdlakha

down counter-372

AryanAdlakha
Profile image for Iishaan

RA2111003011355-Exp10 Down (1)

Iishaan

Creator

Profile image for srm-bintogray

SRM-bintogray

38 Circuits

Date Created

3 years, 10 months ago

Last Modified

3 years, 10 months ago

Tags

  • digital
  • counter

Circuit Copied From

JK - FF& Clock(updown counter)

Related Circuits

Preview of D flip-flop

D flip-flop

by Sobrjery

10846
7
copy
268
Preview of 3-bit Adder

3-bit Adder

by EESal

6184
2
copy
25
Preview of 3-Bit Asynchronous Counter Using D-Flip Flop

3-Bit Asynchronous Counter Using D-Flip Flop

by Angeles_Maila

5520
1
copy
19

Circuit Graph

✕
Graph image for updown counter

Remove Comment

✕

Are you sure you want to remove your comment? This action cannot be undone.

Cancel Remove Comment

✕
Cancel Send

Enter Email

✕