Browser not supported

✕
Go back

Tier limit reached

✕

D flip-flop from NAND gates

0
Favorite
1
copy
Copy
335
Views
Open Circuit
D flip-flop from NAND gates
Social Share
Embed circuit
Embed linked image

Circuit Description

Graph image for D flip-flop from NAND gates

Circuit Graph

D flip-flop created from NAND gates, using clock voltage as the data source. I recommend setting the Grapher time range from 0-5 seconds after running the simulation.

There are currently no comments

Profile image for oraclo

D fliPassaroo-flop from NAND gates (1)

oraclo

Creator

Profile image for oraclo

oraclo

125 Circuits

Date Created

2 years, 9 months ago

Last Modified

2 years, 9 months ago

Tags

  • digital
  • nand gate
  • flip-flop

Circuit Copied From

D flip-flop from NAND gates

Related Circuits

Preview of 4-Bit Digital Counter

4-Bit Digital Counter

by Dayna

28937
16
copy
919
Preview of 3 bit Counter

3 bit Counter

by KWen99

16325
4
copy
160
Preview of Master-Slave D Latch (Edge-Triggered D Flip-Flop) With Preset And Clear

Master-Slave D Latch (Edge-Triggered D Flip-Flop) With Preset And Clear

by GGoodwin

9344
0
copy
31

Circuit Graph

✕
Graph image for D flip-flop from NAND gates

Remove Comment

✕

Are you sure you want to remove your comment? This action cannot be undone.

Cancel Remove Comment

✕
Cancel Send

Enter Email

✕