Initializing Multisim Live ...

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GNDDISOUTRSTVCCTHRCONTRI U14.7kΩRta7.5kΩRtb10kΩRctl0.1μFCt0.01μFCctl5VVcc000001453PR1PR2VoutVout0.1µFCdcplg0 V V
Out of date
V
V
VPP
VRMS
VAV
fV
I
I
IPP
IRMS
IAV
fI
D
Out of date
V
V
VPP
VRMS
VAV
fV
I
I
IPP
IRMS
IAV
fI
D

ID:

ID:

x10
x0.1
Sheet:1
Analysis and annotation
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12345678
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1234567891011121314
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12345
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Netlist
Errors
SPICE
VHDL
SPICE Netlist

This is a text-based representation of the circuit.
The * symbol indicates a comment.
The + symbol indicates a continuation from the previous line.
Probes do not appear in netlists.

** 555 Timer 50% Duty Cycle Astable Multivibrator (Control Voltage Set To ½Vcc) **
*
* Multisim Live SPICE netlist
*
*

* --- Circuit Topology ---

* Component: Cctl
cCctl 3 0 1e-8

* Component: Cdcplg
cCdcplg 5 0 1e-7

* Component: Ct
cCt 1 0 1e-7

* Component: Rctl
rRctl 3 0 10000 VIRTUAL_RESISTANCE_Rctl

* Component: Rta
rRta 5 4 4700 VIRTUAL_RESISTANCE_Rta

* Component: Rtb
rRtb 4 1 7500 VIRTUAL_RESISTANCE_Rtb

* Component: U1
xU1 0 1 Vout 5 3 1 4 5 IDEAL_TIMER_U1

* Component: Vcc
vVcc 5 0 dc 5 ac 0 0
+ distof1 0 0
+ distof2 0 0


* --- Circuit Models ---

* Rctl model
.model VIRTUAL_RESISTANCE_Rctl r( )

* Rta model
.model VIRTUAL_RESISTANCE_Rta r( )

* Rtb model
.model VIRTUAL_RESISTANCE_Rtb r( )


* --- Subcircuits ---

* U1 subcircuit
.subckt IDEAL_TIMER_U1 0 2 3 4 5 6 7 8
rn1 8 5 5k
rn2 5 51 5k
rn3 51 0 5k
Ecomp1 56x 0 value={if(v(5,6)>0,5,0)}
Ecomp2 52x 0 value={if(v(2,51)>0,5,0)}
**These prevent an unstable condition during DC OP
EskipDC 52 0 value={if(TIME>0, v(52x), 0)}
EskipDC2 56 0 value={if(TIME>0, v(56x), 0)}
.model op limit (gain= 3000,
+ out_upper_limit=5,
+ out_lower_limit=-5,
+ limit_range=1 fraction=true)
aadc1 [56 52] [r s] ADC1
.MODEL ADC1 adc_bridge (in_low= 3.5 in_high = 3.5 rise_delay= 1e-12 fall_delay= 1e-12)
anand1 [r Q2] Q1 nand1
anand2 [s Q1] Q2 nand1
.model nand1 d_nand(rise_delay=1n)
adac1 [q1 q2] [66 62] DAC1
rad3 66 0 1
rad4 62 0 1
aadc4 [4] [40] ADC1
ainv2 40 41 inv1
adlatch q1 2u 41 3d Qb Qc dlt
.model dlt d_dlatch(rise_delay=1e-12)
apu1 2u pullup1
.model pullup1 d_pullup(load=10e-12)
apd1 3d pulldown1
.model pulldown1 d_pulldown(load=10e-12)
ainv1 Qb 31 inv1
.model inv1 d_inverter(rise_delay=1e-12)
adac72 [Qb] [72] DAC1
adac31 [31] [32] DAC1
r30 32 0 1g
b1 3 0 v=(v(32)*v(8)/5)
r3 3 0 1g
.MODEL DAC1 dac_bridge (out_low= 0.0 out_high= 5.0 out_undef=0.5)
rad5 72 0 1meg
mdis 7 72 0 0 mdis
.MODEL mdis nmos (VTO=1.29 PHI=0.4 LAMBDA=5 KP=4.3m LD=12.8u GAMMA =3)
.ends

VHDL Netlist

This is a text-based representation of a digital circuit.
The -- symbols indicates a comment.
Probes and analog components do not appear in VHDL netlists.

-- This is a VHDL representation of the -- digital circuit described in the schematic. -- If the circuit described is not valid or is incomplete, -- it may result in an invalid VHDL representation. library IEEE; use IEEE.STD_LOGIC_1164.ALL; USE WORK.ALL; entity top_design is Port ( ); end top_design; architecture BEHAVIORAL of top_design is begin end BEHAVIORAL;
Errors and Warnings

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555 Timer 50% Duty Cycle Astable Multivibrator (Control Voltage Set To ½Vcc)
Schematic

The simulation to run. See Simulation types for more information.

Name

Title of graph. Edit as desired.

Start time

s

Time simulation output is first plotted from. Simulation does not occur in real time.

End time

s

Time at which the simulation stops. Does not include pauses. Simulation does not occur in real time.

Start simulation

Mode

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

V

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

V

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

V

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

V

Output high voltage.

Minimum output voltage level to produce a high signal.

Width

Sheet width in grid squares.

Height

Sheet height in grid squares.

Grid

Toggles grid display.

Net Labels

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Component Labels

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