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D Q ~Q RESET CLK SET D Q ~Q RESET CLK SET D Q ~Q RESET CLK SET D Q ~Q RESET CLK SET 1010 U1U2U3U4InputCLKLED101234560PR1PR2PR3 0/1 0/1 0/1
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ID:

ID:
x10
x0.1
Sheet:1
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SPICE
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SPICE Netlist

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The * symbol indicates a comment.
The + symbol indicates a continuation from the previous line.
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** Shift Registers_SISO **
*
* Multisim Live SPICE netlist
*
*

* --- Circuit Topology ---

* Component: CLK
aCLK 3 Digital_Source_CLK

* Component: Input
aInput 2 Digital_Source_Input

* Component: LED1
xLED1 1 0 LED_VIRTUAL_LED1

* Component: U1
xU1 2 3 U1_NC_SET bridgeU1!RESET 4 U1_NC_~Q Digital_DFlipFlop_U1 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

xbridgeU1!RESET bridgeU1!RESET 0 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=5 riseT=0 fallT=0

* Component: U2
xU2 4 3 U2_NC_SET bridgeU2!RESET 5 U2_NC_~Q Digital_DFlipFlop_U2 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

xbridgeU2!RESET bridgeU2!RESET 0 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=5 riseT=0 fallT=0

* Component: U3
xU3 5 3 U3_NC_SET bridgeU3!RESET 6 U3_NC_~Q Digital_DFlipFlop_U3 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

xbridgeU3!RESET bridgeU3!RESET 0 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=5 riseT=0 fallT=0

* Component: U4
xU4 6 3 U4_NC_SET bridgeU4!RESET bridgeU4!Q U4_NC_~Q Digital_DFlipFlop_U4 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

xbridgeU4!RESET bridgeU4!RESET 0 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=5 riseT=0 fallT=0

xbridgeU4!Q bridgeU4!Q 1 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=5 riseT=0 fallT=0


* --- Circuit Models ---

* CLK model
.model Digital_Source_CLK d_constsource(State=1)

* Input model
.model Digital_Source_Input d_constsource(State=1)


* --- Subcircuits ---

* LED1 subcircuit
.subckt LED_VIRTUAL_LED1 A K

dd1 A 0vNode ledDiodeModel
.model ledDiodeModel D( IS=1e-14 N=1 RS=0 IBV=1e-10 BV=1e+30 CJO=0 M=0.5 VJ=1 )

V_Isense 0vNode K DC 0

* Interactive sense node
b1 lit 0 v = { if (i(V_Isense) < 0, 0, if( i(V_Isense) > 0.005, 1, { i(V_Isense) / 0.005 })) }

.ends

* U1 subcircuit
.subckt Digital_DFlipFlop_U1 1 2 3 4 5 6 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n
*PIN MAPPING: D Q ~Q RESET CLK SET
* 1 5 6 4 2 3
*MODELS USED
aDG1 neg_SR Digital_SourceSR
aDG2 neg_clk Digital_SourceCLK
Axor1 [3 neg_SR] set xor
Axor2 [2 neg_clk] clk xor
Axor3 [4 neg_SR] reset xor
Ajkff 1 clk set reset 5 6 D_FF

.model Digital_SourceCLK d_constsource(State={Negative_Edge_Clock})
.model Digital_SourceSR d_constsource(State={Negative_SET_RESET})
.model xor d_xor
.MODEL D_FF d_dff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS

* U2 subcircuit
.subckt Digital_DFlipFlop_U2 1 2 3 4 5 6 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n
*PIN MAPPING: D Q ~Q RESET CLK SET
* 1 5 6 4 2 3
*MODELS USED
aDG1 neg_SR Digital_SourceSR
aDG2 neg_clk Digital_SourceCLK
Axor1 [3 neg_SR] set xor
Axor2 [2 neg_clk] clk xor
Axor3 [4 neg_SR] reset xor
Ajkff 1 clk set reset 5 6 D_FF

.model Digital_SourceCLK d_constsource(State={Negative_Edge_Clock})
.model Digital_SourceSR d_constsource(State={Negative_SET_RESET})
.model xor d_xor
.MODEL D_FF d_dff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS

* U3 subcircuit
.subckt Digital_DFlipFlop_U3 1 2 3 4 5 6 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n
*PIN MAPPING: D Q ~Q RESET CLK SET
* 1 5 6 4 2 3
*MODELS USED
aDG1 neg_SR Digital_SourceSR
aDG2 neg_clk Digital_SourceCLK
Axor1 [3 neg_SR] set xor
Axor2 [2 neg_clk] clk xor
Axor3 [4 neg_SR] reset xor
Ajkff 1 clk set reset 5 6 D_FF

.model Digital_SourceCLK d_constsource(State={Negative_Edge_Clock})
.model Digital_SourceSR d_constsource(State={Negative_SET_RESET})
.model xor d_xor
.MODEL D_FF d_dff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS

* U4 subcircuit
.subckt Digital_DFlipFlop_U4 1 2 3 4 5 6 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n
*PIN MAPPING: D Q ~Q RESET CLK SET
* 1 5 6 4 2 3
*MODELS USED
aDG1 neg_SR Digital_SourceSR
aDG2 neg_clk Digital_SourceCLK
Axor1 [3 neg_SR] set xor
Axor2 [2 neg_clk] clk xor
Axor3 [4 neg_SR] reset xor
Ajkff 1 clk set reset 5 6 D_FF

.model Digital_SourceCLK d_constsource(State={Negative_Edge_Clock})
.model Digital_SourceSR d_constsource(State={Negative_SET_RESET})
.model xor d_xor
.MODEL D_FF d_dff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS


* --- Pin bridge models

.SUBCKT REAL_CUSTOM_ADC 1 2 PARAMS: lowV=0 maxLowV=0.8 unknownV=1.0 minHighV=2.0 highV=5.0 riseT=0 fallT=0
* Ideal Receiver Model 1 = input, 2 = A/D out
aADCin1 [2] [1] ADC
.MODEL ADC adc_bridge (in_low = {maxLowV} in_high = {minHighV})
.ENDS

.SUBCKT REAL_CUSTOM_DAC 1 2 PARAMS: lowV=0 maxLowV=0.8 unknownV=1.0 minHighV=2.0 highV=5.0 riseT=0 fallT=0
* Ideal Driver Model 1 = A/D out, 2 = input
aDACin1 [1] [2] aDAC
.MODEL aDAC dac_bridge (out_low = {lowV} out_high = {highV} out_undef = {unknownV} t_rise = {max(riseT,1e-9)} t_fall = {max(fallT,1e-9)})
.ENDS
VHDL Netlist

This is a text-based representation of a digital circuit.
The -- symbols indicates a comment.
Probes and analog components do not appear in VHDL netlists.

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY D_FLIP_FLOP IS GENERIC ( ACTIVE_LOW_SET_and_RESET : boolean; Negative_Edge_Trigg_CLOCK : boolean ); PORT ( D : IN STD_LOGIC; SET : IN STD_LOGIC; CLK : IN STD_LOGIC; RESET : IN STD_LOGIC; Q : OUT STD_LOGIC; Qneg : OUT STD_LOGIC ); END ENTITY; ARCHITECTURE BEHAVIORAL OF D_FLIP_FLOP IS BEGIN PROCESS (SET, RESET, CLK) variable CLK_EDGE, LOW, HIGH: std_logic; BEGIN -- Edge trigger polarity CLK_EDGE := '0' when Negative_Edge_Trigg_CLOCK else '1'; -- Set and reset polarity LOW := '1' when ACTIVE_LOW_SET_AND_RESET else '0'; HIGH := '0' when ACTIVE_LOW_SET_AND_RESET else '1'; IF (SET = LOW) AND (RESET = HIGH) THEN Q <= '0'; ELSIF (SET = HIGH) AND (RESET = LOW) THEN Q <= '1'; ELSIF (CLK'event and CLK = CLK_EDGE) THEN Q <= D; END IF; Qneg <= not Q; END PROCESS; END BEHAVIORAL; -- This is a VHDL representation of the -- digital circuit described in the schematic. -- If the circuit described is not valid or is incomplete, -- it may result in an invalid VHDL representation. library IEEE; use IEEE.STD_LOGIC_1164.ALL; USE WORK.ALL; entity top_design is Port ( ); end top_design; architecture BEHAVIORAL of top_design is signal \4\,\5\,\6\ : STD_LOGIC; begin \U1\: entity D_FLIP_FLOP generic map(ACTIVE_LOW_SET_and_RESET => false, Negative_Edge_Trigg_CLOCK => false) port map(CLK => '1', D => '1', Q => \4\, RESET => \0\, SET => open, Qneg => open); \U2\: entity D_FLIP_FLOP generic map(ACTIVE_LOW_SET_and_RESET => false, Negative_Edge_Trigg_CLOCK => false) port map(CLK => '1', D => \4\, Q => \5\, RESET => \0\, SET => open, Qneg => open); \U3\: entity D_FLIP_FLOP generic map(ACTIVE_LOW_SET_and_RESET => false, Negative_Edge_Trigg_CLOCK => false) port map(CLK => '1', D => \5\, Q => \6\, RESET => \0\, SET => open, Qneg => open); \U4\: entity D_FLIP_FLOP generic map(ACTIVE_LOW_SET_and_RESET => false, Negative_Edge_Trigg_CLOCK => false) port map(CLK => '1', D => \6\, Q => \1\, RESET => \0\, SET => open, Qneg => open); end BEHAVIORAL;
Errors and Warnings

Any error, warning or information messages appear below.
TypeDescription
A component update replaced the model for component U1 with a newer version. Check your simulation results.
A component update replaced the model for component U2 with a newer version. Check your simulation results.
A component update replaced the model for component U3 with a newer version. Check your simulation results.
A component update replaced the model for component U4 with a newer version. Check your simulation results.
A component update removed the variable rise_delay from component U1. Check the component to make sure the settings are still correct. The previous value for this variable was 1e-9.
A component update removed the variable fall_delay from component U1. Check the component to make sure the settings are still correct. The previous value for this variable was 1e-9.
A component update removed the variable clk_delay from component U1. Check the component to make sure the settings are still correct. The previous value for this variable was 1e-9.
A component update removed the variable set_delay from component U1. Check the component to make sure the settings are still correct. The previous value for this variable was 1e-9.
A component update removed the variable reset_delay from component U1. Check the component to make sure the settings are still correct. The previous value for this variable was 1e-9.
A component update removed the variable ic from component U1. Check the component to make sure the settings are still correct. The previous value for this variable was 0.
A component update removed the variable rise_delay from component U2. Check the component to make sure the settings are still correct. The previous value for this variable was 1e-9.
A component update removed the variable fall_delay from component U2. Check the component to make sure the settings are still correct. The previous value for this variable was 1e-9.
A component update removed the variable clk_delay from component U2. Check the component to make sure the settings are still correct. The previous value for this variable was 1e-9.
A component update removed the variable set_delay from component U2. Check the component to make sure the settings are still correct. The previous value for this variable was 1e-9.
A component update removed the variable reset_delay from component U2. Check the component to make sure the settings are still correct. The previous value for this variable was 1e-9.
A component update removed the variable ic from component U2. Check the component to make sure the settings are still correct. The previous value for this variable was 0.
A component update removed the variable rise_delay from component U3. Check the component to make sure the settings are still correct. The previous value for this variable was 1e-9.
A component update removed the variable fall_delay from component U3. Check the component to make sure the settings are still correct. The previous value for this variable was 1e-9.
A component update removed the variable clk_delay from component U3. Check the component to make sure the settings are still correct. The previous value for this variable was 1e-9.
A component update removed the variable set_delay from component U3. Check the component to make sure the settings are still correct. The previous value for this variable was 1e-9.
A component update removed the variable reset_delay from component U3. Check the component to make sure the settings are still correct. The previous value for this variable was 1e-9.
A component update removed the variable ic from component U3. Check the component to make sure the settings are still correct. The previous value for this variable was 0.
A component update removed the variable rise_delay from component U4. Check the component to make sure the settings are still correct. The previous value for this variable was 1e-9.
A component update removed the variable fall_delay from component U4. Check the component to make sure the settings are still correct. The previous value for this variable was 1e-9.
A component update removed the variable clk_delay from component U4. Check the component to make sure the settings are still correct. The previous value for this variable was 1e-9.
A component update removed the variable set_delay from component U4. Check the component to make sure the settings are still correct. The previous value for this variable was 1e-9.
A component update removed the variable reset_delay from component U4. Check the component to make sure the settings are still correct. The previous value for this variable was 1e-9.
A component update removed the variable ic from component U4. Check the component to make sure the settings are still correct. The previous value for this variable was 0.
A component update replaced the symbol for component U1 with a newer version. Check your schematic.
A component update replaced the symbol for component U2 with a newer version. Check your schematic.
A component update replaced the symbol for component U3 with a newer version. Check your schematic.
A component update replaced the symbol for component U4 with a newer version. Check your schematic.
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