comparatif 4th Order Low-Pass Sallen-Key Filters

Waiting for data

Signal	Value
Signal	Value

Cursor 1	Cursor 2	∆X	1/∆X	∆Y	∆Y (Phase)

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

Out of date
V	—
V	—
V_PP	—
V_RMS	—
V_AV	—
f_V	—
I	—
I	—
I_PP	—
I_RMS	—
I_AV	—
f_I	—
D	—

ID:

x10

x0.1

Sheet:1

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butterworth

chebyshev

low-pass

active filter

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SPICE

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SPICE Netlist

This is a text-based representation of the circuit.
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** comparatif 4th Order Low-Pass Sallen-Key Filters **
*
* Multisim Live SPICE netlist
*
*

* --- Circuit Topology ---

* Component: C1_b
cC1_b 4 2 1.72e-7

* Component: C1_c
cC1_c 7 6 0.00000105

* Component: C2_b
cC2_b 1 0 1.47e-7

* Component: C2_c
cC2_c 5 0 2.7e-8

* Component: C3_b
cC3_b 11 10 4.16e-7

* Component: C3_c
cC3_c 14 13 7.52e-7

* Component: C4_b
cC4_b 9 0 6.1e-8

* Component: C4_c
cC4_c 12 0 1.13e-7

* Component: R1
rR1 3 2 1000 VIRTUAL_RESISTANCE_R1

* Component: R2
rR2 2 1 1000 VIRTUAL_RESISTANCE_R2

* Component: R3
rR3 8 6 1000 VIRTUAL_RESISTANCE_R3

* Component: R4
rR4 6 5 1000 VIRTUAL_RESISTANCE_R4

* Component: R5
rR5 4 10 1000 VIRTUAL_RESISTANCE_R5

* Component: R6
rR6 10 9 1000 VIRTUAL_RESISTANCE_R6

* Component: R7
rR7 7 13 1000 VIRTUAL_RESISTANCE_R7

* Component: R8
rR8 13 12 1000 VIRTUAL_RESISTANCE_R8

* Component: U1
xU1 1 4 V+ V- 4 5T_VIRTUAL_U1 PARAMS: VOS=0.001 IBS=8e-8 IOS=2e-8 AVOL=200000 BW=100000000 SR=1000000 CMRR=100 ISC=0.025 RI=10000000 RO=10

* Component: U2
xU2 9 11 V+ V- 11 5T_VIRTUAL_U2 PARAMS: VOS=0.001 IBS=8e-8 IOS=2e-8 AVOL=200000 BW=100000000 SR=1000000 CMRR=100 ISC=0.025 RI=10000000 RO=10

* Component: U3
xU3 5 7 V+ V- 7 5T_VIRTUAL_U3 PARAMS: VOS=0.001 IBS=8e-8 IOS=2e-8 AVOL=200000 BW=100000000 SR=1000000 CMRR=100 ISC=0.025 RI=10000000 RO=10

* Component: U4
xU4 12 14 V+ V- 14 5T_VIRTUAL_U4 PARAMS: VOS=0.001 IBS=8e-8 IOS=2e-8 AVOL=200000 BW=100000000 SR=1000000 CMRR=100 ISC=0.025 RI=10000000 RO=10

* Component: V1
vV1 V+ 0 dc 5 ac 0 0
+ distof1 0 0
+ distof2 0 0

* Component: V2
vV2 0 V- dc 5 ac 0 0
+ distof1 0 0
+ distof2 0 0

* Component: V3
vV3 3 0 dc 0 ac 1 0
+ distof1 0 0
+ distof2 0 0
+ sin ( 0 1 1000 0 0 0 )

* Component: V4
vV4 8 0 dc 0 ac 1 0
+ distof1 0 0
+ distof2 0 0
+ sin ( 0 1 1000 0 0 0 )

* --- Circuit Models ---

* R1 model
.model VIRTUAL_RESISTANCE_R1 r( )

* R2 model
.model VIRTUAL_RESISTANCE_R2 r( )

* R3 model
.model VIRTUAL_RESISTANCE_R3 r( )

* R4 model
.model VIRTUAL_RESISTANCE_R4 r( )

* R5 model
.model VIRTUAL_RESISTANCE_R5 r( )

* R6 model
.model VIRTUAL_RESISTANCE_R6 r( )

* R7 model
.model VIRTUAL_RESISTANCE_R7 r( )

* R8 model
.model VIRTUAL_RESISTANCE_R8 r( )

* --- Subcircuits ---

* U1 subcircuit
.subckt 5T_VIRTUAL_U1 In_p In_n Vpos Vneg Out params: AVOL=200k BW=20Meg CMRR=100
+SR=1Meg RO=75 ISC=25m RI=100meg VOS=0.1m IBS=1n IOS=1p
.param Rp1=1e6
.param Rs1=1e6
.param K_Is2a=sqrt(AVOL)/Rs1
.param K_Is2b=sqrt(AVOL)/Rp1
.param Cp1={AVOL/(2*pi*BW*Rp1)}
.param CMRR_lin=10**(CMRR/20)

Rin In_p In_n {RI}
Bcm 4 3 V = { V(cm)/CMRR_lin}
Voff In_p 4 {VOS}
Ibias1 In_p 0 {IBS}
Ibias2 In_n 0 {IBS}
Ioffset In_p In_n {IOS/2}

Rcm1 In_p cm 10meg
Rcm2 In_n cm 10meg

BIs1a vref vs2a I = { K_Is2a*(V(3)-V(In_n)) }
Rs1 vs2a vref {Rs1}

BIs2b vref vs2b I = { K_Is2b*(V(vs2a)-v(vref)) }
Rp1 vs2b vref {Rp1}
VCp1sense vs2b vs2b_ 0
Cp1 vs2b_ vref {Cp1}

D3 vs2b_ 8 Limit_Diode
D4 8 vpos Limit_Diode
B_SRp 8 vpos I={I(VCp1sense)- (Cp1*SR)}

D5 10 vs2b_ Limit_Diode
D6 Vneg 10 Limit_Diode
B_SRn Vneg 10 I={-1*I(VCp1sense)-(Cp1*SR)}

DVpclip vs2b_ Vpos V_limit
DVnclip Vneg vs2b_ V_limit

Bout vref out_ I={(V(vs2b)-v(vref))/RO}
Rout vref out_ {RO}
Voutsense out_ out 0

D9 out 15 Limit_Diode
D10 15 vpos Limit_Diode
B_outp 15 vpos I={I(Voutsense)- ISC}

D11 16 out Limit_Diode
D12 vneg 16 Limit_Diode
B_outn vneg 16 I={-1*I(Voutsense)-ISC}

R5 Vpos mid 1000000
R6 mid Vneg 1000000
Eref vref 0 mid 0 1

.MODEL Limit_Diode D (IS= 1.0e-12)
.MODEL V_limit D(n=0.1)
.ends

* U2 subcircuit
.subckt 5T_VIRTUAL_U2 In_p In_n Vpos Vneg Out params: AVOL=200k BW=20Meg CMRR=100
+SR=1Meg RO=75 ISC=25m RI=100meg VOS=0.1m IBS=1n IOS=1p
.param Rp1=1e6
.param Rs1=1e6
.param K_Is2a=sqrt(AVOL)/Rs1
.param K_Is2b=sqrt(AVOL)/Rp1
.param Cp1={AVOL/(2*pi*BW*Rp1)}
.param CMRR_lin=10**(CMRR/20)

Rin In_p In_n {RI}
Bcm 4 3 V = { V(cm)/CMRR_lin}
Voff In_p 4 {VOS}
Ibias1 In_p 0 {IBS}
Ibias2 In_n 0 {IBS}
Ioffset In_p In_n {IOS/2}

Rcm1 In_p cm 10meg
Rcm2 In_n cm 10meg

BIs1a vref vs2a I = { K_Is2a*(V(3)-V(In_n)) }
Rs1 vs2a vref {Rs1}

BIs2b vref vs2b I = { K_Is2b*(V(vs2a)-v(vref)) }
Rp1 vs2b vref {Rp1}
VCp1sense vs2b vs2b_ 0
Cp1 vs2b_ vref {Cp1}

D3 vs2b_ 8 Limit_Diode
D4 8 vpos Limit_Diode
B_SRp 8 vpos I={I(VCp1sense)- (Cp1*SR)}

D5 10 vs2b_ Limit_Diode
D6 Vneg 10 Limit_Diode
B_SRn Vneg 10 I={-1*I(VCp1sense)-(Cp1*SR)}

DVpclip vs2b_ Vpos V_limit
DVnclip Vneg vs2b_ V_limit

Bout vref out_ I={(V(vs2b)-v(vref))/RO}
Rout vref out_ {RO}
Voutsense out_ out 0

D9 out 15 Limit_Diode
D10 15 vpos Limit_Diode
B_outp 15 vpos I={I(Voutsense)- ISC}

D11 16 out Limit_Diode
D12 vneg 16 Limit_Diode
B_outn vneg 16 I={-1*I(Voutsense)-ISC}

R5 Vpos mid 1000000
R6 mid Vneg 1000000
Eref vref 0 mid 0 1

.MODEL Limit_Diode D (IS= 1.0e-12)
.MODEL V_limit D(n=0.1)
.ends

* U3 subcircuit
.subckt 5T_VIRTUAL_U3 In_p In_n Vpos Vneg Out params: AVOL=200k BW=20Meg CMRR=100
+SR=1Meg RO=75 ISC=25m RI=100meg VOS=0.1m IBS=1n IOS=1p
.param Rp1=1e6
.param Rs1=1e6
.param K_Is2a=sqrt(AVOL)/Rs1
.param K_Is2b=sqrt(AVOL)/Rp1
.param Cp1={AVOL/(2*pi*BW*Rp1)}
.param CMRR_lin=10**(CMRR/20)

Rin In_p In_n {RI}
Bcm 4 3 V = { V(cm)/CMRR_lin}
Voff In_p 4 {VOS}
Ibias1 In_p 0 {IBS}
Ibias2 In_n 0 {IBS}
Ioffset In_p In_n {IOS/2}

Rcm1 In_p cm 10meg
Rcm2 In_n cm 10meg

BIs1a vref vs2a I = { K_Is2a*(V(3)-V(In_n)) }
Rs1 vs2a vref {Rs1}

BIs2b vref vs2b I = { K_Is2b*(V(vs2a)-v(vref)) }
Rp1 vs2b vref {Rp1}
VCp1sense vs2b vs2b_ 0
Cp1 vs2b_ vref {Cp1}

D3 vs2b_ 8 Limit_Diode
D4 8 vpos Limit_Diode
B_SRp 8 vpos I={I(VCp1sense)- (Cp1*SR)}

D5 10 vs2b_ Limit_Diode
D6 Vneg 10 Limit_Diode
B_SRn Vneg 10 I={-1*I(VCp1sense)-(Cp1*SR)}

DVpclip vs2b_ Vpos V_limit
DVnclip Vneg vs2b_ V_limit

Bout vref out_ I={(V(vs2b)-v(vref))/RO}
Rout vref out_ {RO}
Voutsense out_ out 0

D9 out 15 Limit_Diode
D10 15 vpos Limit_Diode
B_outp 15 vpos I={I(Voutsense)- ISC}

D11 16 out Limit_Diode
D12 vneg 16 Limit_Diode
B_outn vneg 16 I={-1*I(Voutsense)-ISC}

R5 Vpos mid 1000000
R6 mid Vneg 1000000
Eref vref 0 mid 0 1

.MODEL Limit_Diode D (IS= 1.0e-12)
.MODEL V_limit D(n=0.1)
.ends

* U4 subcircuit
.subckt 5T_VIRTUAL_U4 In_p In_n Vpos Vneg Out params: AVOL=200k BW=20Meg CMRR=100
+SR=1Meg RO=75 ISC=25m RI=100meg VOS=0.1m IBS=1n IOS=1p
.param Rp1=1e6
.param Rs1=1e6
.param K_Is2a=sqrt(AVOL)/Rs1
.param K_Is2b=sqrt(AVOL)/Rp1
.param Cp1={AVOL/(2*pi*BW*Rp1)}
.param CMRR_lin=10**(CMRR/20)

Rin In_p In_n {RI}
Bcm 4 3 V = { V(cm)/CMRR_lin}
Voff In_p 4 {VOS}
Ibias1 In_p 0 {IBS}
Ibias2 In_n 0 {IBS}
Ioffset In_p In_n {IOS/2}

Rcm1 In_p cm 10meg
Rcm2 In_n cm 10meg

BIs1a vref vs2a I = { K_Is2a*(V(3)-V(In_n)) }
Rs1 vs2a vref {Rs1}

BIs2b vref vs2b I = { K_Is2b*(V(vs2a)-v(vref)) }
Rp1 vs2b vref {Rp1}
VCp1sense vs2b vs2b_ 0
Cp1 vs2b_ vref {Cp1}

D3 vs2b_ 8 Limit_Diode
D4 8 vpos Limit_Diode
B_SRp 8 vpos I={I(VCp1sense)- (Cp1*SR)}

D5 10 vs2b_ Limit_Diode
D6 Vneg 10 Limit_Diode
B_SRn Vneg 10 I={-1*I(VCp1sense)-(Cp1*SR)}

DVpclip vs2b_ Vpos V_limit
DVnclip Vneg vs2b_ V_limit

Bout vref out_ I={(V(vs2b)-v(vref))/RO}
Rout vref out_ {RO}
Voutsense out_ out 0

D9 out 15 Limit_Diode
D10 15 vpos Limit_Diode
B_outp 15 vpos I={I(Voutsense)- ISC}

D11 16 out Limit_Diode
D12 vneg 16 Limit_Diode
B_outn vneg 16 I={-1*I(Voutsense)-ISC}

R5 Vpos mid 1000000
R6 mid Vneg 1000000
Eref vref 0 mid 0 1

.MODEL Limit_Diode D (IS= 1.0e-12)
.MODEL V_limit D(n=0.1)
.ends

VHDL Netlist

This is a text-based representation of a digital circuit.
The -- symbols indicates a comment.
Probes and analog components do not appear in VHDL netlists.

-- This is a VHDL representation of the -- digital circuit described in the schematic. -- If the circuit described is not valid or is incomplete, -- it may result in an invalid VHDL representation. library IEEE; use IEEE.STD_LOGIC_1164.ALL; USE WORK.ALL; entity top_design is Port ( ); end top_design; architecture BEHAVIORAL of top_design is begin end BEHAVIORAL;

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Use document settings

Use logic levels settings from Document tab.

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

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Minimum output voltage level to produce a high signal.

Type Probe

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Function

Use document settings

Use logic levels settings from Document tab.

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

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Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

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Name comparatif 4th Order Low-Pass Sallen-Key Filters

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Absolute voltage error tolerance. Defines the minimum value for voltage where it may still be considered accurate.

ABSTOL

Absolute current error tolerance. Defines the minimum value for current where it may still be considered accurate.

ITL1

DC iteration limit. Number of iterative passes done on DC circuit equations in attempt to reach convergence in simulation.

ITL4

Upper iteration limit. Number of iterative passes done per time point, on Transient circuit equations in attempt to reach convergence in simulation.

Integration method. The numerical integration method used in transient analysis.

Temp

℃

Operating temperature. The temperature at which the entire circuit will be simulated.

Insert shunt resistance

Inserts a resistance of RSHUNT from every analog node to ground. Will aid in convergence, but alter the behavior of the circuit.

RSHUNT

Shunt resistance. This eliminates singular matrix errors that result from a lack of a DC path to ground.

Reset to default

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

Width

Sheet width in grid squares.

Height

Sheet height in grid squares.

Grid

Toggles grid display.

Net Labels

Toggles all net labels.

Component Labels

Toggles all component labels.

comparatif 4th Order Low-Pass Sallen-Key Filters