*DOB PROJECT - Arrik Phatak (1)

Waiting for data

Signal	Value
Signal	Value

Cursor 1	Cursor 2	∆X	1/∆X	∆Y	∆Y (Phase)

ID:

x10

x0.1

Sheet:1

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SPICE

VHDL

SPICE Netlist

This is a text-based representation of the circuit.
The * symbol indicates a comment.
The + symbol indicates a continuation from the previous line.
Probes do not appear in netlists.

** DOB PROJECT - Arrik Phatak (1) **
*
* Multisim Live SPICE netlist
*
*

* --- Circuit Topology ---

* Component: DG1
aDG1 1 Digital_Source_DG1

* Component: U1
xU1 5 bridgeU1!CLK 1 1 31 5 Digital_DFlipFlop_U1 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=1 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

xbridgeU1!CLK bridgeU1!CLK 2 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U10
aU10 [12 31] 13 Digital_NOR2_U10

* Component: U11
aU11 [13 23] 15 Digital_NOR2_U11

* Component: U12
aU12 [15 15] 17 Digital_NOR2_U12

* Component: U13
aU13 [17 26] 16 Digital_NOR2_U13

* Component: U14
aU14 [16 16] bridgeU14!Y Digital_NOR2_U14

xbridgeU14!Y bridgeU14!Y 18 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U15
aU15 [14 14] 21 Digital_NOR2_U15

* Component: U16
aU16 [10 10] 22 Digital_NOR2_U16

* Component: U17
aU17 [21 22] 23 Digital_NOR2_U17

* Component: U18
aU18 [14 14] 25 Digital_NOR2_U18

* Component: U19
aU19 [25 31] 26 Digital_NOR2_U19

* Component: U2
xU2 4 5 1 1 10 4 Digital_DFlipFlop_U2 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=1 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

* Component: U20
aU20 [24 20] 6 Digital_AND2_U20

* Component: U21
aU21 [24 31] 7 Digital_AND2_U21

* Component: U22
aU22 [14 10] 27 Digital_AND2_U22

* Component: U23
aU23 [6 7] 19 Digital_OR2_U23

* Component: U24
aU24 [19 27] bridgeU24!Y Digital_OR2_U24

xbridgeU24!Y bridgeU24!Y 28 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U25
aU25 [14 14] 32 Digital_NAND2_U25

* Component: U26
aU26 [10 10] 33 Digital_NAND2_U26

* Component: U27
aU27 [31 31] 34 Digital_NAND2_U27

* Component: U28
aU28 [32 33] 35 Digital_NAND2_U28

* Component: U29
aU29 [10 31] 36 Digital_NAND2_U29

* Component: U3
xU3 3 4 1 U3_NC_RESET 14 3 Digital_DFlipFlop_U3 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=1 Rise_delay=1e-9 Fall_delay=1e-9 Clk_delay=1e-9 Set_delay=1e-9 Reset_delay=1e-9 Ic=0

* Component: U30
aU30 [14 34] 38 Digital_NAND2_U30

* Component: U31
aU31 [35 36] 37 Digital_NAND2_U31

* Component: U32
aU32 [37 37] 39 Digital_NAND2_U32

* Component: U33
aU33 [39 38] bridgeU33!Y Digital_NAND2_U33

xbridgeU33!Y bridgeU33!Y 40 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U34
aU34 [24 20] 8 Digital_AND2_U34

* Component: U35
aU35 [8 9] 29 Digital_AND2_U35

* Component: U36
aU36 [9 14] 30 Digital_AND2_U36

* Component: U37
aU37 [29 30] bridgeU37!Y Digital_OR2_U37

xbridgeU37!Y bridgeU37!Y 41 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U38
aU38 [24 10] 42 Digital_AND2_U38

* Component: U39
aU39 [42 9] 43 Digital_AND2_U39

* Component: U4
aU4 14 24 Digital_Inverter_U4

* Component: U40
aU40 [14 20] 44 Digital_AND2_U40

* Component: U41
aU41 [14 31] 45 Digital_AND2_U41

* Component: U42
aU42 [43 44] 46 Digital_OR2_U42

* Component: U43
aU43 [46 45] bridgeU43!Y Digital_OR2_U43

xbridgeU43!Y bridgeU43!Y 47 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U5
aU5 10 20 Digital_Inverter_U5

* Component: U6
aU6 31 9 Digital_Inverter_U6

* Component: U7
xU7 18 28 40 18 41 41 47 0 7_SEGMENT_CC_U7

* Component: U8
aU8 [14 10] 11 Digital_NOR2_U8

* Component: U9
aU9 [11 11] 12 Digital_NOR2_U9

* Component: V1
vV1 2 0
+ pulse( 0 5 0 1e-9 1e-9
+ { 50 * 0.01 / 100 }
+ { 1/100 } )

* --- Circuit Models ---

* DG1 model
.model Digital_Source_DG1 d_constsource(State=1)

* U10 model
.model Digital_NOR2_U10 d_nor (rise_delay=1e-9 fall_delay=1e-9)

* U11 model
.model Digital_NOR2_U11 d_nor (rise_delay=1e-9 fall_delay=1e-9)

* U12 model
.model Digital_NOR2_U12 d_nor (rise_delay=1e-9 fall_delay=1e-9)

* U13 model
.model Digital_NOR2_U13 d_nor (rise_delay=1e-9 fall_delay=1e-9)

* U14 model
.model Digital_NOR2_U14 d_nor (rise_delay=1e-9 fall_delay=1e-9)

* U15 model
.model Digital_NOR2_U15 d_nor (rise_delay=1e-9 fall_delay=1e-9)

* U16 model
.model Digital_NOR2_U16 d_nor (rise_delay=1e-9 fall_delay=1e-9)

* U17 model
.model Digital_NOR2_U17 d_nor (rise_delay=1e-9 fall_delay=1e-9)

* U18 model
.model Digital_NOR2_U18 d_nor (rise_delay=1e-9 fall_delay=1e-9)

* U19 model
.model Digital_NOR2_U19 d_nor (rise_delay=1e-9 fall_delay=1e-9)

* U20 model
.model Digital_AND2_U20 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U21 model
.model Digital_AND2_U21 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U22 model
.model Digital_AND2_U22 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U23 model
.model Digital_OR2_U23 d_or (rise_delay=1e-9 fall_delay=1e-9)

* U24 model
.model Digital_OR2_U24 d_or (rise_delay=1e-9 fall_delay=1e-9)

* U25 model
.model Digital_NAND2_U25 d_nand (rise_delay=1e-9 fall_delay=1e-9)

* U26 model
.model Digital_NAND2_U26 d_nand (rise_delay=1e-9 fall_delay=1e-9)

* U27 model
.model Digital_NAND2_U27 d_nand (rise_delay=1e-9 fall_delay=1e-9)

* U28 model
.model Digital_NAND2_U28 d_nand (rise_delay=1e-9 fall_delay=1e-9)

* U29 model
.model Digital_NAND2_U29 d_nand (rise_delay=1e-9 fall_delay=1e-9)

* U30 model
.model Digital_NAND2_U30 d_nand (rise_delay=1e-9 fall_delay=1e-9)

* U31 model
.model Digital_NAND2_U31 d_nand (rise_delay=1e-9 fall_delay=1e-9)

* U32 model
.model Digital_NAND2_U32 d_nand (rise_delay=1e-9 fall_delay=1e-9)

* U33 model
.model Digital_NAND2_U33 d_nand (rise_delay=1e-9 fall_delay=1e-9)

* U34 model
.model Digital_AND2_U34 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U35 model
.model Digital_AND2_U35 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U36 model
.model Digital_AND2_U36 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U37 model
.model Digital_OR2_U37 d_or (rise_delay=1e-9 fall_delay=1e-9)

* U38 model
.model Digital_AND2_U38 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U39 model
.model Digital_AND2_U39 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U4 model
.model Digital_Inverter_U4 d_inverter (rise_delay=1e-9 fall_delay=1e-9)

* U40 model
.model Digital_AND2_U40 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U41 model
.model Digital_AND2_U41 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U42 model
.model Digital_OR2_U42 d_or (rise_delay=1e-9 fall_delay=1e-9)

* U43 model
.model Digital_OR2_U43 d_or (rise_delay=1e-9 fall_delay=1e-9)

* U5 model
.model Digital_Inverter_U5 d_inverter (rise_delay=1e-9 fall_delay=1e-9)

* U6 model
.model Digital_Inverter_U6 d_inverter (rise_delay=1e-9 fall_delay=1e-9)

* U8 model
.model Digital_NOR2_U8 d_nor (rise_delay=1e-9 fall_delay=1e-9)

* U9 model
.model Digital_NOR2_U9 d_nor (rise_delay=1e-9 fall_delay=1e-9)

* --- Subcircuits ---

* U1 subcircuit
.subckt Digital_DFlipFlop_U1 1 2 3 4 5 6 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n
*PIN MAPPING: D Q ~Q RESET CLK SET
* 1 5 6 4 2 3
*MODELS USED
aDG1 neg_SR Digital_SourceSR
aDG2 neg_clk Digital_SourceCLK
Axor1 [3 neg_SR] set xor
Axor2 [2 neg_clk] clk xor
Axor3 [4 neg_SR] reset xor
Ajkff 1 clk set reset 5 6 D_FF

.model Digital_SourceCLK d_constsource(State={Negative_Edge_Clock})
.model Digital_SourceSR d_constsource(State={Negative_SET_RESET})
.model xor d_xor
.MODEL D_FF d_dff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS

* U2 subcircuit
.subckt Digital_DFlipFlop_U2 1 2 3 4 5 6 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n
*PIN MAPPING: D Q ~Q RESET CLK SET
* 1 5 6 4 2 3
*MODELS USED
aDG1 neg_SR Digital_SourceSR
aDG2 neg_clk Digital_SourceCLK
Axor1 [3 neg_SR] set xor
Axor2 [2 neg_clk] clk xor
Axor3 [4 neg_SR] reset xor
Ajkff 1 clk set reset 5 6 D_FF

.model Digital_SourceCLK d_constsource(State={Negative_Edge_Clock})
.model Digital_SourceSR d_constsource(State={Negative_SET_RESET})
.model xor d_xor
.MODEL D_FF d_dff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS

* U3 subcircuit
.subckt Digital_DFlipFlop_U3 1 2 3 4 5 6 PARAMS: Negative_Edge_Clock=0 Negative_SET_RESET=0 Clk_delay=1n Set_delay=1n Reset_delay=1n Ic=0 Rise_delay=1n Fall_delay=1n
*PIN MAPPING: D Q ~Q RESET CLK SET
* 1 5 6 4 2 3
*MODELS USED
aDG1 neg_SR Digital_SourceSR
aDG2 neg_clk Digital_SourceCLK
Axor1 [3 neg_SR] set xor
Axor2 [2 neg_clk] clk xor
Axor3 [4 neg_SR] reset xor
Ajkff 1 clk set reset 5 6 D_FF

.model Digital_SourceCLK d_constsource(State={Negative_Edge_Clock})
.model Digital_SourceSR d_constsource(State={Negative_SET_RESET})
.model xor d_xor
.MODEL D_FF d_dff (clk_delay={Clk_delay} set_delay={Set_delay} reset_delay={Reset_delay} ic={Ic} rise_delay={Rise_delay} fall_delay={Fall_delay})
.ENDS

* U7 subcircuit
.subckt 7_SEGMENT_CC_U7 A1 A2 A3 A4 A5 A6 A7 K

dd1 A1 0vNode1 ledDiodeModel
Vsense1 0vNode1 K DC 0
* Interactive sense node
b1 lit1 0 v = { if (i(Vsense1) < 0, 0, if( i(Vsense1) > 0.02, 1, { i(Vsense1) / 0.02 })) }

dd2 A2 0vNode2 ledDiodeModel
Vsense2 0vNode2 K DC 0
* Interactive sense node
b2 lit2 0 v = { if (i(Vsense2) < 0, 0, if( i(Vsense2) > 0.02, 1, { i(Vsense2) / 0.02 })) }

dd3 A3 0vNode3 ledDiodeModel
Vsense3 0vNode3 K DC 0
* Interactive sense node
b3 lit3 0 v = { if (i(Vsense3) < 0, 0, if( i(Vsense3) > 0.02, 1, { i(Vsense3) / 0.02 })) }

dd4 A4 0vNode4 ledDiodeModel
Vsense4 0vNode4 K DC 0
* Interactive sense node
b4 lit4 0 v = { if (i(Vsense4) < 0, 0, if( i(Vsense4) > 0.02, 1, { i(Vsense4) / 0.02 })) }

dd5 A5 0vNode5 ledDiodeModel
Vsense5 0vNode5 K DC 0
* Interactive sense node
b5 lit5 0 v = { if (i(Vsense5) < 0, 0, if( i(Vsense5) > 0.02, 1, { i(Vsense5) / 0.02 })) }

dd6 A6 0vNode6 ledDiodeModel
Vsense6 0vNode6 K DC 0
* Interactive sense node
b6 lit6 0 v = { if (i(Vsense6) < 0, 0, if( i(Vsense6) > 0.02, 1, { i(Vsense6) / 0.02 })) }

dd7 A7 0vNode7 ledDiodeModel
Vsense7 0vNode7 K DC 0
* Interactive sense node
b7 lit7 0 v = { if (i(Vsense7) < 0, 0, if( i(Vsense7) > 0.02, 1, { i(Vsense7) / 0.02 })) }

.model ledDiodeModel D( IS=1e-14 N=1 RS=0 IBV=1e-10 BV=1e+30 CJO=0 M=0.5 VJ=1 )
.ends

* --- Pin bridge models

.SUBCKT REAL_CUSTOM_ADC 1 2 PARAMS: lowV=0 maxLowV=0.8 unknownV=1.0 minHighV=2.0 highV=5.0 riseT=0 fallT=0
* Ideal Receiver Model 1 = input, 2 = A/D out
aADCin1 [2] [1] ADC
.MODEL ADC adc_bridge (in_low = {maxLowV} in_high = {minHighV})
.ENDS

.SUBCKT REAL_CUSTOM_DAC 1 2 PARAMS: lowV=0 maxLowV=0.8 unknownV=1.0 minHighV=2.0 highV=5.0 riseT=0 fallT=0
* Ideal Driver Model 1 = A/D out, 2 = input
aDACin1 [1] [2] aDAC
.MODEL aDAC dac_bridge (out_low = {lowV} out_high = {highV} out_undef = {unknownV} t_rise = {max(riseT,1e-9)} t_fall = {max(fallT,1e-9)})
.ENDS

VHDL Netlist

This is a text-based representation of a digital circuit.
The -- symbols indicates a comment.
Probes and analog components do not appear in VHDL netlists.

-- This is a VHDL representation of the -- digital circuit described in the schematic. -- If the circuit described is not valid or is incomplete, -- it may result in an invalid VHDL representation. library IEEE; use IEEE.STD_LOGIC_1164.ALL; USE WORK.ALL; entity top_design is Port ( ); end top_design; architecture BEHAVIORAL of top_design is signal \3\,\4\,\5\,\11\,\12\,\13\,\15\,\16\,\17\,\20\,\21\,\22\,\23\,\24\,\25\,\26\,\6\,\7\,\19\,\27\,\31\,\32\,\33\,\34\,\35\,\36\,\37\,\38\,\39\,\10\,\14\,\8\,\9\,\29\,\30\,\42\,\43\,\44\,\45\,\46\ : STD_LOGIC; begin end BEHAVIORAL;

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Item

Document

Section

Only one section is available for multisection components.

Type

Rise time

Time it takes for signal to transition from low to high.

With non-zero rise time, the signal converts to an analog signal from a digital signal.

Fall time

Time it takes for signal to transition from high to low.

With non-zero fall time, the signal converts to an analog signal from a digital signal.

Use document settings

Use logic levels settings from Document tab.

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

Type Probe

Select desired function.

Function

Use document settings

Use logic levels settings from Document tab.

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

Enter an expression here. You can combine circuit variables with functions and operators to plot an expression in the Grapher.

Available functions, constants and operators for the expression.

Source

Data origin.

…

Upload a data file here. You can view data from this file in the grapher.

Web address of the selected Source.

Warning: A popup window will appear.

Connect

Cancel

Connecting

Disconnect

Switch on to stream data from Source when simulation runs.

For data files with more than one plot, select the plot to view.

Source type

Application used to generate the Source data.

Data type

Type of simulation data in Source.

File size

Size of the referenced file. Total file size for all data plotters cannot exceed 100 MB.

Selected simulation type does not match uploaded simulation data

Data streaming is only available in interactive simulation

Instantaneous

Displays instantaneous measurements on probe during interactive simulation.

Periodic

Displays periodic measurements on probe during Interactive simulation.

Bias point(s)

Displays bias points on probe for DC Op simulation.

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Name DOB PROJECT - Arrik Phatak (1)

Type Schematic

The simulation to run. See Simulation types for more information.

Name

Title of graph. Edit as desired.

End time

Time at which the simulation stops. Does not include pauses. Simulation does not occur in real time.

Start simulation

RELTOL

Relative error tolerance. A simulation wide accuracy control used to establish convergence.

VNTOL

Absolute voltage error tolerance. Defines the minimum value for voltage where it may still be considered accurate.

ABSTOL

Absolute current error tolerance. Defines the minimum value for current where it may still be considered accurate.

ITL1

DC iteration limit. Number of iterative passes done on DC circuit equations in attempt to reach convergence in simulation.

ITL4

Upper iteration limit. Number of iterative passes done per time point, on Transient circuit equations in attempt to reach convergence in simulation.

Integration method. The numerical integration method used in transient analysis.

Temp

℃

Operating temperature. The temperature at which the entire circuit will be simulated.

Insert shunt resistance

Inserts a resistance of RSHUNT from every analog node to ground. Will aid in convergence, but alter the behavior of the circuit.

RSHUNT

Shunt resistance. This eliminates singular matrix errors that result from a lack of a DC path to ground.

Reset to default

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

Width

Sheet width in grid squares.

Height

Sheet height in grid squares.

Grid

Toggles grid display.

Net Labels

Toggles all net labels.

Component Labels

Toggles all component labels.

DOB PROJECT - Arrik Phatak (1)