Browser not supported

✕
Go back

Tier limit reached

✕

SISO SHIFT REGISTER 3-BIT

0
Favorite
2
copy
Copy
250
Views
Open Circuit
SISO SHIFT REGISTER 3-BIT
Social Share
Embed circuit
Embed linked image

Circuit Description

Graph image for SISO SHIFT REGISTER 3-BIT

Circuit Graph

D flip-flop created from NAND gates, using clock voltage as the data source. I recommend setting the Grapher time range from 0-5 seconds after running the simulation.

There are currently no comments

Profile image for Chaitanya942

PISO SHIFT REGISTER 3-BIT

Chaitanya942
Profile image for Chaitanya942

SIPO SHIFT REGISTER 3-BIT (1)

Chaitanya942

Creator

Profile image for chaitanya942

Chaitanya942

24 Circuits

Date Created

2 years, 4 months ago

Last Modified

2 years, 4 months ago

Tags

  • digital
  • nand gate
  • flip-flop

Circuit Copied From

D flip-flop

Related Circuits

Preview of 4-Bit Digital Counter

4-Bit Digital Counter

by Dayna

27950
15
copy
919
Preview of 3 bit Counter

3 bit Counter

by KWen99

15980
4
copy
158
Preview of Master-Slave D Latch (Edge-Triggered D Flip-Flop) With Preset And Clear

Master-Slave D Latch (Edge-Triggered D Flip-Flop) With Preset And Clear

by GGoodwin

8909
0
copy
30

Circuit Graph

✕
Graph image for SISO SHIFT REGISTER 3-BIT

Remove Comment

✕

Are you sure you want to remove your comment? This action cannot be undone.

Cancel Remove Comment

✕
Cancel Send

Enter Email

✕