J-K Latch

This is a J-K latch with active high Enable (C), the functions are below: NO CHANGE: J=0, K=0 RESET: J=0, K=1 SET: J=1, K=0 With J and K both high, Q and NOTQ will be both high when C is high, Q and NOTQ will toggle fast when C is low. The 100 kΩ load resistors are not part of the J-K Latch, their purpose is to help initialize the output to known logic state. At the start of simulation the output signals will always be toggling fast regardless of J and K if C is initially low. With C initially high, toggling also occurs with J and K both equal to 0. While these conditions can be exited, faster initialization can be obtained with C high and J=0, K=1 or J=1, K=0.