*3.2.2 (a)

Waiting for data

Signal	Value
Signal	Value

Cursor 1	Cursor 2	∆X	1/∆X	∆Y	∆Y (Phase)

ID:

x10

x0.1

Sheet:1

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** 3.2.2 (a) **
*
* Multisim Live SPICE netlist
*
*

* --- Circuit Topology ---

* Component: BD1
aBD1 [bridgeBD1!A bridgeBD1!B] 4 Digital_AND2_BD1

xbridgeBD1!A bridgeBD1!A AB2Bit REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeBD1!B bridgeBD1!B ADLSB REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: BNOTC1
aBNOTC1 [bridgeBNOTC1!A 49] 47 Digital_AND2_BNOTC1

xbridgeBNOTC1!A bridgeBNOTC1!A AB2Bit REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: BNOTCD1
aBNOTCD1 [bridgeBNOTCD1!A 47] 36 Digital_AND2_BNOTCD1

xbridgeBNOTCD1!A bridgeBNOTCD1!A ADLSB REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: BNOTD1
aBNOTD1 [bridgeBNOTD1!A 34] 37 Digital_AND2_BNOTD1

xbridgeBNOTD1!A bridgeBNOTD1!A AB2Bit REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: CD1
aCD1 [bridgeCD1!A bridgeCD1!B] 32 Digital_AND2_CD1

xbridgeCD1!A bridgeCD1!A AC1Bit REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeCD1!B bridgeCD1!B ADLSB REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: CNOTD1
aCNOTD1 [bridgeCNOTD1!A 34] 38 Digital_AND2_CNOTD1

xbridgeCNOTD1!A bridgeCNOTD1!A AC1Bit REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: DG1
aDG1 5 Digital_Source_DG1

* Component: DG4
aDG4 bridgeDG4!OUT Digital_Source_DG4

xbridgeDG4!OUT bridgeDG4!OUT 46 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: LED1
xLED1 ADLSB 0 LED_VIRTUAL_LED1

* Component: LED2
xLED2 AC1Bit 0 LED_VIRTUAL_LED2

* Component: LED3
xLED3 AB2Bit 0 LED_VIRTUAL_LED3

* Component: NOTBC1
aNOTBC1 [48 bridgeNOTBC1!B] 35 Digital_AND2_NOTBC1

xbridgeNOTBC1!B bridgeNOTBC1!B AC1Bit REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: NOTBNOTD1
aNOTBNOTD1 [48 34] 29 Digital_AND2_NOTBNOTD1

* Component: NOTCNOTD1
aNOTCNOTD1 [49 34] 33 Digital_AND2_NOTCNOTD1

* Component: U1
aU1 2 bridgeU1!CLK 9 bridgeU1!RESET bridgeU1!Q 2 Digital_DFlipFlop_U1

xbridgeU1!CLK bridgeU1!CLK 1 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU1!RESET bridgeU1!RESET 0 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU1!Q bridgeU1!Q ADLSB REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U11
aU11 bridgeU11!A 48 Digital_Inverter_U11

xbridgeU11!A bridgeU11!A AB2Bit REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U12
aU12 bridgeU12!A 49 Digital_Inverter_U12

xbridgeU12!A bridgeU12!A AC1Bit REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U14
aU14 bridgeU14!A 34 Digital_Inverter_U14

xbridgeU14!A bridgeU14!A ADLSB REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U18
xU18 39 40 41 42 43 44 45 46 7_SEGMENT_CC_U18

* Component: U2
aU2 7 2 bridgeU2!SET 9 bridgeU2!Q 7 Digital_DFlipFlop_U2

xbridgeU2!SET bridgeU2!SET 0 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU2!Q bridgeU2!Q AC1Bit REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U3
aU3 8 7 bridgeU3!SET 9 bridgeU3!Q 8 Digital_DFlipFlop_U3

xbridgeU3!SET bridgeU3!SET 0 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU3!Q bridgeU3!Q AB2Bit REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U4
aU4 [5 3 bridgeU4!C bridgeU4!D] 9 Digital_AND4_U4

xbridgeU4!C bridgeU4!C AC1Bit REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeU4!D bridgeU4!D AB2Bit REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U5
aU5 bridgeU5!A 3 Digital_Inverter_U5

xbridgeU5!A bridgeU5!A ADLSB REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: U7
aU7 bridgeU7!A U7_NC_Y Digital_Inverter_U7

xbridgeU7!A bridgeU7!A 0 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: V1
vV1 1 0
+ pulse( 0 5 0 1e-9 1e-9
+ { 50 * 0.01 / 1000 }
+ { 1/1000 } )

* Component: a1
aa1 [4 29 bridgea1!C bridgea1!D] bridgea1!Y Digital_OR4_a1

xbridgea1!C bridgea1!C 0 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgea1!D bridgea1!D AC1Bit REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgea1!Y bridgea1!Y 39 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: b1
ab1 [32 48 33] bridgeb1!Y Digital_OR3_b1

xbridgeb1!Y bridgeb1!Y 40 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: c1
ac1 [bridgec1!A 49 bridgec1!C] bridgec1!Y Digital_OR3_c1

xbridgec1!A bridgec1!A AB2Bit REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgec1!C bridgec1!C ADLSB REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgec1!Y bridgec1!Y 41 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: d1
ad1 [bridged1!A 29 38 35 36] bridged1!Y Digital_OR5_d1

xbridged1!A bridged1!A 0 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridged1!Y bridged1!Y 42 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: e1
ae1 [38 29] bridgee1!Y Digital_OR2_e1

xbridgee1!Y bridgee1!Y 43 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: f1
af1 [33 47 37 bridgef1!D] bridgef1!Y Digital_OR4_f1

xbridgef1!D bridgef1!D 0 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgef1!Y bridgef1!Y 44 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* Component: g1
ag1 [38 35 bridgeg1!C 47] bridgeg1!Y Digital_OR4_g1

xbridgeg1!C bridgeg1!C 0 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

xbridgeg1!Y bridgeg1!Y 45 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=3.3 riseT=0 fallT=0

* --- Circuit Models ---

* BD1 model
.model Digital_AND2_BD1 d_and (rise_delay=1e-9 fall_delay=1e-9)

* BNOTC1 model
.model Digital_AND2_BNOTC1 d_and (rise_delay=1e-9 fall_delay=1e-9)

* BNOTCD1 model
.model Digital_AND2_BNOTCD1 d_and (rise_delay=1e-9 fall_delay=1e-9)

* BNOTD1 model
.model Digital_AND2_BNOTD1 d_and (rise_delay=1e-9 fall_delay=1e-9)

* CD1 model
.model Digital_AND2_CD1 d_and (rise_delay=1e-9 fall_delay=1e-9)

* CNOTD1 model
.model Digital_AND2_CNOTD1 d_and (rise_delay=1e-9 fall_delay=1e-9)

* DG1 model
.model Digital_Source_DG1 d_constsource(State=1)

* DG4 model
.model Digital_Source_DG4 d_constsource(State=0)

* NOTBC1 model
.model Digital_AND2_NOTBC1 d_and (rise_delay=1e-9 fall_delay=1e-9)

* NOTBNOTD1 model
.model Digital_AND2_NOTBNOTD1 d_and (rise_delay=1e-9 fall_delay=1e-9)

* NOTCNOTD1 model
.model Digital_AND2_NOTCNOTD1 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U1 model
.model Digital_DFlipFlop_U1 d_dff (rise_delay=1e-9 fall_delay=1e-9 clk_delay=1e-9 set_delay=1e-9 reset_delay=1e-9 ic=0)

* U11 model
.model Digital_Inverter_U11 d_inverter (rise_delay=1e-9 fall_delay=1e-9)

* U12 model
.model Digital_Inverter_U12 d_inverter (rise_delay=1e-9 fall_delay=1e-9)

* U14 model
.model Digital_Inverter_U14 d_inverter (rise_delay=1e-9 fall_delay=1e-9)

* U2 model
.model Digital_DFlipFlop_U2 d_dff (rise_delay=1e-9 fall_delay=1e-9 clk_delay=1e-9 set_delay=1e-9 reset_delay=1e-9 ic=0)

* U3 model
.model Digital_DFlipFlop_U3 d_dff (rise_delay=1e-9 fall_delay=1e-9 clk_delay=1e-9 set_delay=1e-9 reset_delay=1e-9 ic=0)

* U4 model
.model Digital_AND4_U4 d_and (rise_delay=1e-9 fall_delay=1e-9)

* U5 model
.model Digital_Inverter_U5 d_inverter (rise_delay=1e-9 fall_delay=1e-9)

* U7 model
.model Digital_Inverter_U7 d_inverter (rise_delay=1e-9 fall_delay=1e-9)

* a1 model
.model Digital_OR4_a1 d_or (rise_delay=1e-9 fall_delay=1e-9)

* b1 model
.model Digital_OR3_b1 d_or (rise_delay=1e-9 fall_delay=1e-9)

* c1 model
.model Digital_OR3_c1 d_or (rise_delay=1e-9 fall_delay=1e-9)

* d1 model
.model Digital_OR5_d1 d_or (rise_delay=1e-9 fall_delay=1e-9)

* e1 model
.model Digital_OR2_e1 d_or (rise_delay=1e-9 fall_delay=1e-9)

* f1 model
.model Digital_OR4_f1 d_or (rise_delay=1e-9 fall_delay=1e-9)

* g1 model
.model Digital_OR4_g1 d_or (rise_delay=1e-9 fall_delay=1e-9)

* --- Subcircuits ---

* LED1 subcircuit
.subckt LED_VIRTUAL_LED1 A K

dd1 A 0vNode ledDiodeModel
.model ledDiodeModel D( IS=1e-14 N=1 RS=0 IBV=1e-10 BV=1e+30 CJO=0 M=0.5 VJ=1 )

V_Isense 0vNode K DC 0

* Interactive sense node
b1 lit 0 v = { if (i(V_Isense) < 0, 0, if( i(V_Isense) > 0.005, 1, { i(V_Isense) / 0.005 })) }

.ends

* LED2 subcircuit
.subckt LED_VIRTUAL_LED2 A K

dd1 A 0vNode ledDiodeModel
.model ledDiodeModel D( IS=1e-14 N=1 RS=0 IBV=1e-10 BV=1e+30 CJO=0 M=0.5 VJ=1 )

V_Isense 0vNode K DC 0

* Interactive sense node
b1 lit 0 v = { if (i(V_Isense) < 0, 0, if( i(V_Isense) > 0.005, 1, { i(V_Isense) / 0.005 })) }

.ends

* LED3 subcircuit
.subckt LED_VIRTUAL_LED3 A K

dd1 A 0vNode ledDiodeModel
.model ledDiodeModel D( IS=1e-14 N=1 RS=0 IBV=1e-10 BV=1e+30 CJO=0 M=0.5 VJ=1 )

V_Isense 0vNode K DC 0

* Interactive sense node
b1 lit 0 v = { if (i(V_Isense) < 0, 0, if( i(V_Isense) > 0.005, 1, { i(V_Isense) / 0.005 })) }

.ends

* U18 subcircuit
.subckt 7_SEGMENT_CC_U18 A1 A2 A3 A4 A5 A6 A7 K

dd1 A1 0vNode1 ledDiodeModel
Vsense1 0vNode1 K DC 0
* Interactive sense node
b1 lit1 0 v = { if (i(Vsense1) < 0, 0, if( i(Vsense1) > 0.02, 1, { i(Vsense1) / 0.02 })) }

dd2 A2 0vNode2 ledDiodeModel
Vsense2 0vNode2 K DC 0
* Interactive sense node
b2 lit2 0 v = { if (i(Vsense2) < 0, 0, if( i(Vsense2) > 0.02, 1, { i(Vsense2) / 0.02 })) }

dd3 A3 0vNode3 ledDiodeModel
Vsense3 0vNode3 K DC 0
* Interactive sense node
b3 lit3 0 v = { if (i(Vsense3) < 0, 0, if( i(Vsense3) > 0.02, 1, { i(Vsense3) / 0.02 })) }

dd4 A4 0vNode4 ledDiodeModel
Vsense4 0vNode4 K DC 0
* Interactive sense node
b4 lit4 0 v = { if (i(Vsense4) < 0, 0, if( i(Vsense4) > 0.02, 1, { i(Vsense4) / 0.02 })) }

dd5 A5 0vNode5 ledDiodeModel
Vsense5 0vNode5 K DC 0
* Interactive sense node
b5 lit5 0 v = { if (i(Vsense5) < 0, 0, if( i(Vsense5) > 0.02, 1, { i(Vsense5) / 0.02 })) }

dd6 A6 0vNode6 ledDiodeModel
Vsense6 0vNode6 K DC 0
* Interactive sense node
b6 lit6 0 v = { if (i(Vsense6) < 0, 0, if( i(Vsense6) > 0.02, 1, { i(Vsense6) / 0.02 })) }

dd7 A7 0vNode7 ledDiodeModel
Vsense7 0vNode7 K DC 0
* Interactive sense node
b7 lit7 0 v = { if (i(Vsense7) < 0, 0, if( i(Vsense7) > 0.02, 1, { i(Vsense7) / 0.02 })) }

.model ledDiodeModel D( IS=1e-14 N=1 RS=0 IBV=1e-10 BV=1e+30 CJO=0 M=0.5 VJ=1 )
.ends

* --- Pin bridge models

.SUBCKT REAL_CUSTOM_ADC 1 2 PARAMS: lowV=0 maxLowV=0.8 unknownV=1.0 minHighV=2.0 highV=5.0 riseT=0 fallT=0
* Ideal Receiver Model 1 = input, 2 = A/D out
aADCin1 [2] [1] ADC
.MODEL ADC adc_bridge (in_low = {maxLowV} in_high = {minHighV})
.ENDS

.SUBCKT REAL_CUSTOM_DAC 1 2 PARAMS: lowV=0 maxLowV=0.8 unknownV=1.0 minHighV=2.0 highV=5.0 riseT=0 fallT=0
* Ideal Driver Model 1 = A/D out, 2 = input
aDACin1 [1] [2] aDAC
.MODEL aDAC dac_bridge (out_low = {lowV} out_high = {highV} out_undef = {unknownV} t_rise = {max(riseT,1e-9)} t_fall = {max(fallT,1e-9)})
.ENDS

VHDL Netlist

This is a text-based representation of a digital circuit.
The -- symbols indicates a comment.
Probes and analog components do not appear in VHDL netlists.

-- This is a VHDL representation of the -- digital circuit described in the schematic. -- If the circuit described is not valid or is incomplete, -- it may result in an invalid VHDL representation. library IEEE; use IEEE.STD_LOGIC_1164.ALL; USE WORK.ALL; entity top_design is Port ( ); end top_design; architecture BEHAVIORAL of top_design is signal \4\,\29\,\32\,\33\,\35\,\36\,\37\,\38\,\47\,\34\,\48\,\49\,\2\,\7\,\8\,\9\,\3\ : STD_LOGIC; begin end BEHAVIORAL;

Errors and Warnings

Any error, warning or information messages appear below.

Item

Document

Section

Only one section is available for multisection components.

Type

Rise time

Time it takes for signal to transition from low to high.

With non-zero rise time, the signal converts to an analog signal from a digital signal.

Fall time

Time it takes for signal to transition from high to low.

With non-zero fall time, the signal converts to an analog signal from a digital signal.

Use document settings

Use logic levels settings from Document tab.

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

Type Probe

Select desired function.

Function

Use document settings

Use logic levels settings from Document tab.

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

Enter an expression here. You can combine circuit variables with functions and operators to plot an expression in the Grapher.

Available functions, constants and operators for the expression.

Source

Data origin.

…

Upload a data file here. You can view data from this file in the grapher.

Web address of the selected Source.

Warning: A popup window will appear.

Connect

Cancel

Connecting

Disconnect

Switch on to stream data from Source when simulation runs.

For data files with more than one plot, select the plot to view.

Source type

Application used to generate the Source data.

Data type

Type of simulation data in Source.

File size

Size of the referenced file. Total file size for all data plotters cannot exceed 100 MB.

Selected simulation type does not match uploaded simulation data

Data streaming is only available in interactive simulation

Instantaneous

Displays instantaneous measurements on probe during interactive simulation.

Periodic

Displays periodic measurements on probe during Interactive simulation.

Bias point(s)

Displays bias points on probe for DC Op simulation.

No items selected.

Name 3.2.2 (a)

Type Schematic

The simulation to run. See Simulation types for more information.

Name

Title of graph. Edit as desired.

End time

Time at which the simulation stops. Does not include pauses. Simulation does not occur in real time.

Start simulation

RELTOL

Relative error tolerance. A simulation wide accuracy control used to establish convergence.

VNTOL

Absolute voltage error tolerance. Defines the minimum value for voltage where it may still be considered accurate.

ABSTOL

Absolute current error tolerance. Defines the minimum value for current where it may still be considered accurate.

ITL1

DC iteration limit. Number of iterative passes done on DC circuit equations in attempt to reach convergence in simulation.

ITL4

Upper iteration limit. Number of iterative passes done per time point, on Transient circuit equations in attempt to reach convergence in simulation.

Integration method. The numerical integration method used in transient analysis.

Temp

℃

Operating temperature. The temperature at which the entire circuit will be simulated.

Insert shunt resistance

Inserts a resistance of RSHUNT from every analog node to ground. Will aid in convergence, but alter the behavior of the circuit.

RSHUNT

Shunt resistance. This eliminates singular matrix errors that result from a lack of a DC path to ground.

Reset to default

Threshold voltage levels.

Threshold voltage values used in the logic evaluation. See Digital Simulation for more information.

Output low

Output low voltage.

Maximum output voltage level to produce a low signal.

Input low threshold

Input low threshold voltage.

Maximum input voltage level for the signal to be considered low.

Input high threshold

Input high threshold voltage.

Minimum input voltage level for the signal to be considered high.

Output high

Output high voltage.

Minimum output voltage level to produce a high signal.

Width

Sheet width in grid squares.

Height

Sheet height in grid squares.

Grid

Toggles grid display.

Net Labels

Toggles all net labels.

Component Labels

Toggles all component labels.

3.2.2 (a)