JK Flip-Flop (NAND Logic)

This is a CMOS JK Flip-Flop that is essentially a modified version of an SR-Latch. It is built from cross-coupled CMOS NAND gate circuits. ⚠️ The Toggle action where inputs, C, J, K are all High is presently not working properly. Some redesign is needed. 📚 Action taken by Flip-Flop is to either Set, Reset, Toggle, or Hold it's present value depending on the K, J, and Clock (C) inputs. 📖 JK Flip-Flop Operation C | J | K | Action | Q | Q̄ | ✔ | 0 | 0 | Hold | - | - | ✔ | 0 | 1 | Reset | 0 | 1 | ✔ | 1 | 0 | Set | 1 | 0 | ✔ | 1 | 1 | Toggle | 🔃 | 🔃 | ------------------------------------ ❌ | 0 | 0 | Hold | - | - | ❌ | 0 | 1 | Hold | - | - | ❌ | 1 | 0 | Hold | - | - | ❌ | 1 | 1 | Hold | - | - |