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ID:

ID:
x10
x0.1
Sheet:1
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** RA1911027010130_EXPT_9_SIPO **
*
* Multisim Live SPICE netlist
*
*

* --- Circuit Topology ---

* Component: DG1
aDG1 3 Digital_Source_DG1

* Component: DG2
aDG2 4 Digital_Source_DG2

* Component: LED1
xLED1 6 0 LED_VIRTUAL_LED1

* Component: LED2
xLED2 5 0 LED_VIRTUAL_LED2

* Component: LED3
xLED3 2 0 LED_VIRTUAL_LED3

* Component: LED4
xLED4 1 0 LED_VIRTUAL_LED4

* Component: U1
aU1 3 4 U1_NC_SET bridgeU1!RESET bridgeU1!Q U1_NC_~Q Digital_DFlipFlop_U1

xbridgeU1!RESET bridgeU1!RESET 0 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=5 riseT=0 fallT=0

xbridgeU1!Q bridgeU1!Q 1 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=5 riseT=0 fallT=0

* Component: U2
aU2 bridgeU2!D 4 U2_NC_SET bridgeU2!RESET bridgeU2!Q U2_NC_~Q Digital_DFlipFlop_U2

xbridgeU2!D bridgeU2!D 1 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=5 riseT=0 fallT=0

xbridgeU2!RESET bridgeU2!RESET 0 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=5 riseT=0 fallT=0

xbridgeU2!Q bridgeU2!Q 2 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=5 riseT=0 fallT=0

* Component: U3
aU3 bridgeU3!D 4 U3_NC_SET bridgeU3!RESET bridgeU3!Q U3_NC_~Q Digital_DFlipFlop_U3

xbridgeU3!D bridgeU3!D 2 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=5 riseT=0 fallT=0

xbridgeU3!RESET bridgeU3!RESET 0 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=5 riseT=0 fallT=0

xbridgeU3!Q bridgeU3!Q 5 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=5 riseT=0 fallT=0

* Component: U4
aU4 bridgeU4!D 4 U4_NC_SET bridgeU4!RESET bridgeU4!Q U4_NC_~Q Digital_DFlipFlop_U4

xbridgeU4!D bridgeU4!D 5 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=5 riseT=0 fallT=0

xbridgeU4!RESET bridgeU4!RESET 0 REAL_CUSTOM_ADC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=5 riseT=0 fallT=0

xbridgeU4!Q bridgeU4!Q 6 REAL_CUSTOM_DAC PARAMS: lowV=0 maxLowV=0.8 unknownV=1 minHighV=2 highV=5 riseT=0 fallT=0


* --- Circuit Models ---

* DG1 model
.model Digital_Source_DG1 d_constsource(State=1)

* DG2 model
.model Digital_Source_DG2 d_constsource(State=1)

* U1 model
.model Digital_DFlipFlop_U1 d_dff (rise_delay=1e-9 fall_delay=1e-9 clk_delay=1e-9 set_delay=1e-9 reset_delay=1e-9 ic=0)

* U2 model
.model Digital_DFlipFlop_U2 d_dff (rise_delay=1e-9 fall_delay=1e-9 clk_delay=1e-9 set_delay=1e-9 reset_delay=1e-9 ic=0)

* U3 model
.model Digital_DFlipFlop_U3 d_dff (rise_delay=1e-9 fall_delay=1e-9 clk_delay=1e-9 set_delay=1e-9 reset_delay=1e-9 ic=0)

* U4 model
.model Digital_DFlipFlop_U4 d_dff (rise_delay=1e-9 fall_delay=1e-9 clk_delay=1e-9 set_delay=1e-9 reset_delay=1e-9 ic=0)


* --- Subcircuits ---

* LED1 subcircuit
.subckt LED_VIRTUAL_LED1 A K

dd1 A 0vNode ledDiodeModel
.model ledDiodeModel D( IS=1e-14 N=1 RS=0 IBV=1e-10 BV=1e+30 CJO=0 M=0.5 VJ=1 )

V_Isense 0vNode K DC 0

* Interactive sense node
b1 lit 0 v = { if (i(V_Isense) < 0, 0, if( i(V_Isense) > 0.005, 1, { i(V_Isense) / 0.005 })) }

.ends

* LED2 subcircuit
.subckt LED_VIRTUAL_LED2 A K

dd1 A 0vNode ledDiodeModel
.model ledDiodeModel D( IS=1e-14 N=1 RS=0 IBV=1e-10 BV=1e+30 CJO=0 M=0.5 VJ=1 )

V_Isense 0vNode K DC 0

* Interactive sense node
b1 lit 0 v = { if (i(V_Isense) < 0, 0, if( i(V_Isense) > 0.005, 1, { i(V_Isense) / 0.005 })) }

.ends

* LED3 subcircuit
.subckt LED_VIRTUAL_LED3 A K

dd1 A 0vNode ledDiodeModel
.model ledDiodeModel D( IS=1e-14 N=1 RS=0 IBV=1e-10 BV=1e+30 CJO=0 M=0.5 VJ=1 )

V_Isense 0vNode K DC 0

* Interactive sense node
b1 lit 0 v = { if (i(V_Isense) < 0, 0, if( i(V_Isense) > 0.005, 1, { i(V_Isense) / 0.005 })) }

.ends

* LED4 subcircuit
.subckt LED_VIRTUAL_LED4 A K

dd1 A 0vNode ledDiodeModel
.model ledDiodeModel D( IS=1e-14 N=1 RS=0 IBV=1e-10 BV=1e+30 CJO=0 M=0.5 VJ=1 )

V_Isense 0vNode K DC 0

* Interactive sense node
b1 lit 0 v = { if (i(V_Isense) < 0, 0, if( i(V_Isense) > 0.005, 1, { i(V_Isense) / 0.005 })) }

.ends


* --- Pin bridge models

.SUBCKT REAL_CUSTOM_ADC 1 2 PARAMS: lowV=0 maxLowV=0.8 unknownV=1.0 minHighV=2.0 highV=5.0 riseT=0 fallT=0
* Ideal Receiver Model 1 = input, 2 = A/D out
aADCin1 [2] [1] ADC
.MODEL ADC adc_bridge (in_low = {maxLowV} in_high = {minHighV})
.ENDS

.SUBCKT REAL_CUSTOM_DAC 1 2 PARAMS: lowV=0 maxLowV=0.8 unknownV=1.0 minHighV=2.0 highV=5.0 riseT=0 fallT=0
* Ideal Driver Model 1 = A/D out, 2 = input
aDACin1 [1] [2] aDAC
.MODEL aDAC dac_bridge (out_low = {lowV} out_high = {highV} out_undef = {unknownV} t_rise = {max(riseT,1e-9)} t_fall = {max(fallT,1e-9)})
.ENDS
VHDL Netlist

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-- This is a VHDL representation of the -- digital circuit described in the schematic. -- If the circuit described is not valid or is incomplete, -- it may result in an invalid VHDL representation. library IEEE; use IEEE.STD_LOGIC_1164.ALL; USE WORK.ALL; entity top_design is Port ( ); end top_design; architecture BEHAVIORAL of top_design is begin end BEHAVIORAL;
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RA1911027010130_EXPT_9_SIPO
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